公开(公告)号：US11688704B2

公开(公告)日：2023-06-27

申请号：US17580961

申请日：2022-01-21

Applicant: Futurewei Technologies, Inc.

Inventor： Shiqun Gu ,  Jinghua Zhu ,  Hongying Zhang ,  Jun Xia ,  Wangsheng Xie ,  Shuangfu Wang ,  Hong Liu ,  Liming Zhao ,  Hongquan Sun

IPC: H01L29/739 ,  H01L23/00 ,  H01L21/78 ,  H01L23/29 ,  H01L21/48 ,  H01L25/00 ,  H01L25/10 ,  H01L21/683 ,  H01L25/065 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L24/06 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/293 ,  H01L24/03 ,  H01L24/11 ,  H01L24/14 ,  H01L24/81 ,  H01L25/105 ,  H01L25/50 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2221/68304 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/81005 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058

Abstract: An integrated circuit package and a system including the integrated circuit package as well as a process for assembling the integrated circuit package are provided to improve integrated circuit power delivery. The integrated circuit package includes a first die having a plurality of pads formed in the first die and exposed on a top surface of the first die, at least one post on the first die, and a substrate including one or more redistribution layers. Each post in the at least one post spans at least two pads on the first die utilized for power distribution, and the first die is connected to the substrate via the at least one post.

公开(公告)号：US11233025B2

公开(公告)日：2022-01-25

申请号：US15880451

申请日：2018-01-25

Applicant: Futurewei Technologies, Inc.

Inventor： Shiqun Gu ,  Jinghua Zhu ,  Hongying Zhang ,  Jun Xia ,  Wangsheng Xie ,  Shuangfu Wang ,  Hong Liu ,  Liming Zhao ,  Hongquan Sun

IPC: H01L29/00 ,  H01L23/00 ,  H01L21/78 ,  H01L23/29 ,  H01L21/48 ,  H01L25/00 ,  H01L25/10 ,  H01L21/683 ,  H01L25/065 ,  H01L23/498 ,  H01L23/31

Abstract: An integrated circuit package and a system including the integrated circuit package as well as a process for assembling the integrated circuit package are provided to improve integrated circuit power delivery. The integrated circuit package includes a first die having a plurality of pads formed in the first die and exposed on a top surface of the first die, at least one post on the first die, and a substrate including one or more redistribution layers. Each post in the at least one post spans at least two pads on the first die utilized for power distribution, and the first die is connected to the substrate via the at least one post.

公开(公告)号：US20190273060A1

公开(公告)日：2019-09-05

申请号：US16414304

申请日：2019-05-16

Applicant: FUTUREWEI TECHNOLOGIES, INC.

Inventor： Shiqun Gu ,  Hongying Zhang ,  HongLiang Cai

IPC: H01L23/00 ,  H01L21/768

Abstract: A packaged Integrated Circuit (IC) includes an IC and a package. The package has a bottom dielectric layer and a plurality of redistribution layers (RDLs) formed on the bottom dielectric layer. Each the RDLs includes patterned conductors, a dielectric layer, and a plurality of vias that extend between the patterned conductors to a differing RDL or to external connections. The package includes a plurality of package pads that have a first lateral separation pitch. The IC includes a plurality of IC pads that electrically connect to the plurality of package pads that have a first lateral separation pitch. The package also includes a plurality of Printed Circuit Board (PCB) pads that extend through the bottom dielectric layer and contact the plurality of patterned conductors of the first RDL. Power PCB pads and ground PCB pads of the plurality of PCB pads have a second lateral separation pitch that exceeds the first lateral separation pitch.

公开(公告)号：US20190148323A1

公开(公告)日：2019-05-16

申请号：US15814736

申请日：2017-11-16

Applicant: Futurewei Technologies, Inc.

Inventor： Shiqun Gu ,  Hongying Zhang ,  HongLiang Cai

IPC: H01L23/00 ,  H01L21/768

Abstract: A packaged Integrated Circuit (IC) includes an IC and a package. The package has a bottom dielectric layer and a plurality of redistribution layers (RDLs) formed on the bottom dielectric layer. Each the RDLs includes patterned conductors, a dielectric layer, and a plurality of vias that extend between the patterned conductors to a differing RDL or to external connections. The package includes a plurality of package pads that have a first lateral separation pitch. The IC includes a plurality of IC pads that electrically connect to the plurality of package pads that have a first lateral separation pitch. The package also includes a plurality of Printed Circuit Board (PCB) pads that extend through the bottom dielectric layer and contact the plurality of patterned conductors of the first RDL. Power PCB pads and ground PCB pads of the plurality of PCB pads have a second lateral separation pitch that exceeds the first lateral separation pitch.

公开(公告)号：US10658335B2

公开(公告)日：2020-05-19

申请号：US15880455

申请日：2018-01-25

Applicant: Futurewei Technologies, Inc.

Inventor： Shiqun Gu ,  Yu Lin ,  Jinghua Zhu ,  Guofang Jiao

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/10 ,  H01L23/64

Abstract: An integrated circuit package and a system including the integrated circuit package as well as a process for assembling the integrated circuit package are provided. The integrated circuit package includes a first die manufactured on a first wafer utilizing a first node size, a second die manufactured on a second wafer utilizing a second node size, and a substrate coupled to the second die at a plurality of bump sites on a bottom surface of the second die. The first die may be mounted on a top surface of the second die utilizing a hybrid wafer bonding technique, micro bumps, or electrode-less plating.

公开(公告)号：US20180366442A1

公开(公告)日：2018-12-20

申请号：US15880455

申请日：2018-01-25

Applicant: Futurewei Technologies, Inc.

Inventor： Shiqun Gu ,  Yu Lin ,  Jinghua Zhu ,  Guofang Jiao

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00

Abstract: An integrated circuit package and a system including the integrated circuit package as well as a process for assembling the integrated circuit package are provided. The integrated circuit package includes a first die manufactured on a first wafer utilizing a first node size, a second die manufactured on a second wafer utilizing a second node size, and a substrate coupled to the second die at a plurality of bump sites on a bottom surface of the second die. The first die may be mounted on a top surface of the second die utilizing a hybrid wafer bonding technique, micro bumps, or electrode-less plating.

公开(公告)号：US11101224B2

公开(公告)日：2021-08-24

申请号：US15877283

申请日：2018-01-22

Applicant: Futurewei Technologies, Inc.

Inventor： Shiqun Gu ,  Tiejun Liu ,  Zhao Chen

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/522 ,  H01L21/768 ,  H01L23/498

Abstract: Techniques and structures for improving shielding of an integrated circuit package are provided. The integrated circuit package includes a die including a plurality of bump sites and a substrate connected to the die at the plurality of bump sites. The substrate includes at least one layer that implements one or more signal traces and a plurality of shield traces. Each shield trace in the plurality of shield traces is coupled to a ground plane by a plurality of slot vias.

公开(公告)号：US10304792B1

公开(公告)日：2019-05-28

申请号：US15814736

申请日：2017-11-16

Applicant: Futurewei Technologies, Inc.

Inventor： Shiqun Gu ,  Hongying Zhang ,  HongLiang Cai

IPC: H01L21/44 ,  H01L23/00 ,  H01L21/768

Abstract: A packaged Integrated Circuit (IC) includes an IC and a package. The package has a bottom dielectric layer and a plurality of redistribution layers (RDLs) formed on the bottom dielectric layer. Each the RDLs includes patterned conductors, a dielectric layer, and a plurality of vias that extend between the patterned conductors to a differing RDL or to external connections. The package includes a plurality of package pads that have a first lateral separation pitch. The IC includes a plurality of IC pads that electrically connect to the plurality of package pads that have a first lateral separation pitch. The package also includes a plurality of Printed Circuit Board (PCB) pads that extend through the bottom dielectric layer and contact the plurality of patterned conductors of the first RDL. Power PCB pads and ground PCB pads of the plurality of PCB pads have a second lateral separation pitch that exceeds the first lateral separation pitch.

公开(公告)号：US20180358303A1

公开(公告)日：2018-12-13

申请号：US15877283

申请日：2018-01-22

Applicant: Futurewei Technologies, Inc.

Inventor： Shiqun Gu ,  Tiejun Liu ,  Zhao Chen

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/522 ,  H01L23/498 ,  H01L21/768

CPC classification number: H01L23/552 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/49827 ,  H01L23/5226 ,  H01L24/14 ,  H01L24/17 ,  H01L2924/14 ,  H01L2924/15321 ,  H01L2924/3025

Abstract: Techniques and structures for improving shielding of an integrated circuit package are provided. The integrated circuit package includes a die including a plurality of bump sites and a substrate connected to the die at the plurality of bump sites. The substrate includes at least one layer that implements one or more signal traces and a plurality of shield traces. Each shield trace in the plurality of shield traces is coupled to a ground plane by a plurality of slot vias.

公开(公告)号：US20180350762A1

公开(公告)日：2018-12-06

申请号：US15880451

申请日：2018-01-25

Applicant: Futurewei Technologies, Inc.

Inventor： Shiqun Gu ,  Jinghua Zhu ,  Hongying Zhang ,  Jun Xia ,  Wangsheng Xie ,  Shuangfu Wang ,  Hong Liu ,  Liming Zhao ,  Hongquan Sun

IPC: H01L23/00 ,  H01L21/78 ,  H01L25/00 ,  H01L23/29 ,  H01L21/48 ,  H01L25/065

Abstract: An integrated circuit package and a system including the integrated circuit package as well as a process for assembling the integrated circuit package are provided to improve integrated circuit power delivery. The integrated circuit package includes a first die having a plurality of pads formed in the first die and exposed on a top surface of the first die, at least one post on the first die, and a substrate including one or more redistribution layers. Each post in the at least one post spans at least two pads on the first die utilized for power distribution, and the first die is connected to the substrate via the at least one post.