公开(公告)号：US20160300788A1

公开(公告)日：2016-10-13

申请号：US14684664

申请日：2015-04-13

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Rahul Agarwal ,  Jens Oswald ,  Sheng Feng Lu ,  Soon Leng Tan ,  Jeffrey Lam

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/66 ,  G01R31/04

CPC classification number: H01L23/49827 ,  G01R31/04 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/6835 ,  H01L22/14 ,  H01L23/147 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68372

Abstract: A method of forming and testing an interposer includes forming vias in a semiconductor material of a wafer having a front side and a back side. The method further includes disposing an electrically conductive layer on the front side of the wafer such that the layer is electrically connected to the vias. The method also includes forming electrically conductive pads on the front side of the wafer, wherein each electrically conductive pad is electrically connected to the electrically conductive layer. The method further includes forming electrically conductive bumps on the back side of the wafer, wherein each electrically conductive bump is electrically connected to at least one via. The method also includes testing electrical connectivity from a first bump to a second bump of the electrically conductive bumps.

Abstract translation: 形成和测试插入件的方法包括在具有正面和背面的晶片的半导体材料中形成通孔。 该方法还包括在晶片的前侧设置导电层，使得该层电连接到通孔。 该方法还包括在晶片的正面上形成导电焊盘，其中每个导电焊盘电连接到导电层。 该方法还包括在晶片的背面形成导电凸块，其中每个导电凸块与至少一个通孔电连接。 该方法还包括测试从导电凸块的第一凸起到第二凸块的电连接。

公开(公告)号：US09601424B2

公开(公告)日：2017-03-21

申请号：US14684664

申请日：2015-04-13

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Rahul Agarwal ,  Jens Oswald ,  Sheng Feng Lu ,  Soon Leng Tan ,  Jeffrey Lam

IPC: H01L21/48 ,  H01L21/66 ,  H01L23/498 ,  G01R31/04

CPC classification number: H01L23/49827 ,  G01R31/04 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/6835 ,  H01L22/14 ,  H01L23/147 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68372

Abstract: A method of forming and testing an interposer includes forming vias in a semiconductor material of a wafer having a front side and a back side. The method further includes disposing an electrically conductive layer on the front side of the wafer such that the layer is electrically connected to the vias. The method also includes forming electrically conductive pads on the front side of the wafer, wherein each electrically conductive pad is electrically connected to the electrically conductive layer. The method further includes forming electrically conductive bumps on the back side of the wafer, wherein each electrically conductive bump is electrically connected to at least one via. The method also includes testing electrical connectivity from a first bump to a second bump of the electrically conductive bumps.