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    Backside spacer structures for improved thermal performance
    1.
    发明授权
    Backside spacer structures for improved thermal performance 有权

    公开(公告)号：US10153224B2

    公开(公告)日：2018-12-11

    申请号：US15264957

    申请日：2016-09-14

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Rahul Agarwal ,  Luke England ,  Haojun Zhang

    IPC: H01L23/367 ,  H01L23/00 ,  H01L21/288

    Abstract: Methods for reducing the junction temperature between an IC chip and its lid by including metal spacers in the TIM layer and the resulting devices are disclosed. Embodiments include providing a substrate, including integrated circuit devices, having front and back sides; forming vertical spacers on the backside of the substrate; providing a plate parallel to and spaced from the backside of the substrate; and forming a TIM layer, surrounding the vertical spacers, between the backside of the substrate and the plate.

    Method of manufacturing a 3 color LED integrated Si CMOS driver wafer using die to wafer bonding approach
    3.
    发明授权
    Method of manufacturing a 3 color LED integrated Si CMOS driver wafer using die to wafer bonding approach 有权

    公开(公告)号：US10193011B1

    公开(公告)日：2019-01-29

    申请号：US15650427

    申请日：2017-07-14

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Srinivasa Banna ,  Deepak Nayak ,  Luke England ,  Rahul Agarwal

    IPC: H01L27/30 ,  H01L31/18 ,  H01L27/15

    Abstract: Methods of forming an integrated RGB LED and Si CMOS driver wafer and the resulting devices are provided. Embodiments include providing a plurality of first color die over a CMOS wafer, each first color die being laterally separated with a first oxide and electrically connected to the CMOS wafer; providing a second color die above each first color die, each second color die being separated from each other with a second oxide, bonded to a first color die, and electrically connected to the CMOS wafer through the bonded first color die; removing a portion of each second color die to expose a portion of each bonded first color die; forming a conformal TCO layer over each first and second color die and on a side surface of each second color die and oxide; forming a PECVD oxide layer over the CMOS wafer; and planarizing the PECVD oxide layer.

    CRACKSTOPS FOR BULK SEMICONDUCTOR WAFERS
    6.
    发明申请
    CRACKSTOPS FOR BULK SEMICONDUCTOR WAFERS 审中-公开
    用于大块半导体波形的裂纹

    公开(公告)号：US20150371956A1

    公开(公告)日：2015-12-24

    申请号：US14309024

    申请日：2014-06-19

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Rahul Agarwal ,  Shun Qiang Gong

    IPC: H01L23/00 ,  H01L21/283 ,  H01L21/3065

    CPC classification number: H01L23/562 ,  H01L21/02019 ,  H01L21/02021 ,  H01L21/3065 ,  H01L21/76898 ,  H01L21/78 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Embodiments of the present invention provide crackstops for bulk semiconductor wafers and methods of fabrication. A die level crackstop is formed as a trench within the wafer around each die. A wafer level crackstop includes one or more trenches formed as rings around the periphery of the wafer near the wafer edge. These crackstops serve to prevent damage during handling of ultra thin wafers and dicing of individual ICs, thereby improving product yield.

    Abstract translation: 本发明的实施例为块状半导体晶片提供裂缝和制造方法。 模具级裂缝形成为围绕每个模具的晶片内的沟槽。 晶片级裂缝包括在晶片边缘附近围绕晶片周边形成的环形成一个或多个沟槽。 这些裂缝用于防止在处理超薄晶片和切割各个IC时的损坏，从而提高产品产量。

    INTERPOSER AND METHODS OF FORMING AND TESTING AN INTERPOSER
    8.
    发明申请
    INTERPOSER AND METHODS OF FORMING AND TESTING AN INTERPOSER 有权
    插入物和插入物的形成和测试方法

    公开(公告)号：US20160300788A1

    公开(公告)日：2016-10-13

    申请号：US14684664

    申请日：2015-04-13

    Applicant: GLOBALFOUNDRIES, INC.

    Inventor： Rahul Agarwal ,  Jens Oswald ,  Sheng Feng Lu ,  Soon Leng Tan ,  Jeffrey Lam

    IPC: H01L23/498 ,  H01L21/48 ,  H01L21/66 ,  G01R31/04

    CPC classification number: H01L23/49827 ,  G01R31/04 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/6835 ,  H01L22/14 ,  H01L23/147 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68372

    Abstract: A method of forming and testing an interposer includes forming vias in a semiconductor material of a wafer having a front side and a back side. The method further includes disposing an electrically conductive layer on the front side of the wafer such that the layer is electrically connected to the vias. The method also includes forming electrically conductive pads on the front side of the wafer, wherein each electrically conductive pad is electrically connected to the electrically conductive layer. The method further includes forming electrically conductive bumps on the back side of the wafer, wherein each electrically conductive bump is electrically connected to at least one via. The method also includes testing electrical connectivity from a first bump to a second bump of the electrically conductive bumps.

    Abstract translation: 形成和测试插入件的方法包括在具有正面和背面的晶片的半导体材料中形成通孔。 该方法还包括在晶片的前侧设置导电层，使得该层电连接到通孔。 该方法还包括在晶片的正面上形成导电焊盘，其中每个导电焊盘电连接到导电层。 该方法还包括在晶片的背面形成导电凸块，其中每个导电凸块与至少一个通孔电连接。 该方法还包括测试从导电凸块的第一凸起到第二凸块的电连接。

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