公开(公告)号：US20140327140A1

公开(公告)日：2014-11-06

申请号：US13887174

申请日：2013-05-03

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Xunyuan Zhang ,  Xuan Lin ,  Vimal Kamineni

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L23/53266 ,  H01L21/28562 ,  H01L21/31144 ,  H01L21/32134 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76849 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes providing a semiconductor substrate disposed with a device therein and/or thereon. A contact structure including a barrier layer and a plug metal overlying the barrier layer is formed in electrical contact with the device. A hardmask is formed overlying the contact structure. The method includes performing an etch to form a via opening through the hardmask and to expose the barrier layer and the plug metal. Further, the method removes a remaining portion of the hardmask with a wet etchant, while the contact structure is configured to inhibit the wet etchant from etching the barrier layer. In the method, the via opening is filled with a conductive material to form an interconnect to the contact structure.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在示例性实施例中，用于制造集成电路的方法包括提供在其中和/或其上设置有器件的半导体衬底。 包括阻挡层和覆盖阻挡层的插塞金属的接触结构形成为与器件电接触。 覆盖接触结构的硬掩模形成。 该方法包括执行蚀刻以形成通过硬掩模的通孔，并暴露阻挡层和插塞金属。 此外，该方法用湿蚀刻剂去除硬掩模的剩余部分，而接触结构被配置为抑制湿蚀刻剂蚀刻阻挡层。 在该方法中，通孔开口填充有导电材料以形成与接触结构的互连。

公开(公告)号：US09040421B2

公开(公告)日：2015-05-26

申请号：US13887174

申请日：2013-05-03

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xunyuan Zhang ,  Xuan Lin ,  Vimal Kamineni

IPC: H01L21/44 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L23/53266 ,  H01L21/28562 ,  H01L21/31144 ,  H01L21/32134 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76849 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes providing a semiconductor substrate disposed with a device therein and/or thereon. A contact structure including a barrier layer and a plug metal overlying the barrier layer is formed in electrical contact with the device. A hardmask is formed overlying the contact structure. The method includes performing an etch to form a via opening through the hardmask and to expose the barrier layer and the plug metal. Further, the method removes a remaining portion of the hardmask with a wet etchant, while the contact structure is configured to inhibit the wet etchant from etching the barrier layer. In the method, the via opening is filled with a conductive material to form an interconnect to the contact structure.

Abstract translation: 提供了制造集成电路的方法。 在示例性实施例中，用于制造集成电路的方法包括提供在其中和/或其上设置有器件的半导体衬底。 包括阻挡层和覆盖阻挡层的插塞金属的接触结构形成为与器件电接触。 覆盖接触结构的硬掩模形成。 该方法包括执行蚀刻以形成通过硬掩模的通孔，并暴露阻挡层和插塞金属。 此外，该方法用湿蚀刻剂去除硬掩模的剩余部分，而接触结构被配置为抑制湿蚀刻剂蚀刻阻挡层。 在该方法中，通孔开口填充有导电材料以形成与接触结构的互连。

公开(公告)号：US09287213B2

公开(公告)日：2016-03-15

申请号：US14695965

申请日：2015-04-24

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xunyuan Zhang ,  Xuan Lin ,  Vimal Kamineni

IPC: H01L21/31 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L23/53266 ,  H01L21/28562 ,  H01L21/31144 ,  H01L21/32134 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76849 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits with improved contact structures are provided. In an exemplary embodiment, an integrated circuit includes a semiconductor substrate disposed with a device therein and/or thereon. The integrated circuit includes a contact structure in electrical contact with the device. The contact structure includes a plug metal and a barrier layer, and the barrier layer is selected from fluorine-free tungsten (FFW), tungsten carbide, and tungsten nitride. The integrated circuit further includes a dielectric material overlying the semiconductor substrate. Also, the integrated circuit includes an interconnect formed within the dielectric material and in electrical contact with the contact structure.

Abstract translation: 提供了具有改进的接触结构的集成电路。 在示例性实施例中，集成电路包括在其中和/或其上设置有设备的半导体衬底。 集成电路包括与器件电接触的接触结构。 接触结构包括插塞金属和阻挡层，阻挡层选自无氟钨（FFW），碳化钨和氮化钨。 集成电路还包括覆盖半导体衬底的电介质材料。 此外，集成电路包括形成在电介质材料内并与接触结构电接触的互连。