公开(公告)号：US20140021579A1

公开(公告)日：2014-01-23

申请号：US14032484

申请日：2013-09-20

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Randy W. Mann ,  Kingsuk Maitra ,  Anurag Mittal

IPC: H01L23/62

CPC classification number: H01L23/62 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of fabricating an integrated circuit with a fin-based fuse, and the resulting integrated circuit with a fin-based fuse are provided. In the method, a fin is created from a layer of semiconductor material and has a first end and a second end. The method provides for forming a conductive path on the fin from its first end to its second end. The conductive path is electrically connected to a programming device that is capable of selectively directing a programming current through the conductive path to cause a structural change in the conductive path to increase resistance across the conductive path.

Abstract translation: 提供了制造具有鳍式保险丝的集成电路的方法，以及所得到的具有鳍式保险丝的集成电路。 在该方法中，由半导体材料层产生翅片并具有第一端和第二端。 该方法提供了在翅片上从其第一端到其第二端形成导电路径。 导电路径电连接到编程设备，该编程设备能够选择性地将编程电流引导通过导电路径，从而导致导电路径中的结构变化，以增加穿过导电路径的电阻。

公开(公告)号：US08963255B2

公开(公告)日：2015-02-24

申请号：US14219910

申请日：2014-03-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jeremy A. Wahl ,  Kingsuk Maitra

IPC: H01L29/76 ,  H01L29/94

CPC classification number: H01L27/092 ,  H01L21/26506 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/66651 ,  H01L29/78

Abstract: A semiconductor is formed on a (110) silicon (Si) substrate, with improved electron mobility. Embodiments include semiconductor devices having a silicon carbide (SiC) portion in the nFET channel region. An embodiment includes forming an nFET channel region and a pFET channel region in a Si substrate, such as a (110) Si substrate, and forming a silicon carbide (SiC) portion on the nFET channel region. The SiC portion may be formed by ion implantation of C followed by a recrystallization anneal or by epitaxial growth of SiC in a recess formed in the substrate. The use of SiC in the nFET channel region improves electron mobility without introducing topographical differences between NMOS and PMOS transistors.

Abstract translation: 在（110）硅（Si）衬底上形成半导体，具有改善的电子迁移率。 实施例包括在nFET沟道区域中具有碳化硅（SiC）部分的半导体器件。 一个实施例包括在诸如（110）Si衬底的Si衬底中形成nFET沟道区和pFET沟道区，并在nFET沟道区上形成碳化硅（SiC）部分。 SiC部分可以通过C的离子注入，然后通过在衬底中形成的凹陷中的SiC再结晶退火或外延生长来形成。 在nFET通道区域中使用SiC可以提高电子迁移率，而不会导致NMOS和PMOS晶体管之间的形貌差异。

公开(公告)号：US09219040B2

公开(公告)日：2015-12-22

申请号：US14032484

申请日：2013-09-20

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Randy W. Mann ,  Kingsuk Maitra ,  Anurag Mittal

IPC: H01L23/525 ,  H01L23/62

CPC classification number: H01L23/62 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of fabricating an integrated circuit with a fin-based fuse, and the resulting integrated circuit with a fin-based fuse are provided. In the method, a fin is created from a layer of semiconductor material and has a first end and a second end. The method provides for forming a conductive path on the fin from its first end to its second end. The conductive path is electrically connected to a programming device that is capable of selectively directing a programming current through the conductive path to cause a structural change in the conductive path to increase resistance across the conductive path.

Abstract translation: 提供了制造具有鳍式保险丝的集成电路的方法，以及所得到的具有鳍式保险丝的集成电路。 在该方法中，由半导体材料层产生翅片并具有第一端和第二端。 该方法提供了在翅片上从其第一端到其第二端形成导电路径。 导电路径电连接到编程设备，该编程设备能够选择性地将编程电流引导通过导电路径，从而导致导电路径中的结构变化，以增加穿过导电路径的电阻。