公开(公告)号：US09252131B2

公开(公告)日：2016-02-02

申请号：US14051067

申请日：2013-10-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Edgar R. Cordero ,  Anand Haridass ,  Subrat K. Panda ,  Saravanan Sethuraman ,  Diyanesh Babu Chinnakkonda Vidyapoornachary

IPC: G06F12/08 ,  H01L25/065 ,  G06F11/00 ,  H01L25/07

CPC classification number: H01L25/0657 ,  G06F11/00 ,  G06F12/0802 ,  H01L25/071 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: By arranging dies in a stack such that failed cores are aligned with adjacent good cores, fast connections between good cores and cache of failed cores can be implemented. Cache can be allocated according to a priority assigned to each good core, by latency between a requesting core and available cache, and/or by load on a core.

Abstract translation: 通过将堆叠中的模具排列成使得故障核心与相邻的良好核心对齐，可以实现良好内核与故障核心缓存之间的快速连接。 可以根据分配给每个好核心的优先级，通过请求内核与可用缓存之间的延迟和/或通过核心上的负载来分配缓存。