公开(公告)号：US09952500B2

公开(公告)日：2018-04-24

申请号：US15239072

申请日：2016-08-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sudeep Mandal ,  Arun S. Mampazhy

IPC: G06F17/50 ,  G03F1/36

CPC classification number: G03F1/36 ,  G06F17/5081

Abstract: Embodiments of the present disclosure include methods, program products, and systems for adjusting an integrated circuit (IC) layout for optical proximity correction (OPC). Methods according to the disclosure can include: defining a target region of the IC design layout, the target region having a plurality of patterns including a first pattern positioned adjacent to a second pattern, wherein an OPC modeling rule of the IC design layout prohibits the first pattern from being adjusted, and wherein the second pattern does not reduce a printability metric of the first pattern; adjusting the design of the second pattern to reduce at least one printing error in the first pattern, wherein a functionality of the second pattern in the IC design layout is unchanged after the adjusting; and implementing OPC on the IC design layout including the target region with the adjusted second pattern therein.

公开(公告)号：US20180052388A1

公开(公告)日：2018-02-22

申请号：US15239072

申请日：2016-08-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sudeep Mandal ,  Arun S. Mampazhy

IPC: G03F1/36 ,  G06F17/50

CPC classification number: G03F1/36 ,  G06F17/5081

Abstract: Embodiments of the present disclosure include methods, program products, and systems for adjusting an integrated circuit (IC) layout for optical proximity correction (OPC). Methods according to the disclosure can include: defining a target region of the IC design layout, the target region having a plurality of patterns including a first pattern positioned adjacent to a second pattern, wherein an OPC modeling rule of the IC design layout prohibits the first pattern from being adjusted, and wherein the second pattern does not reduce a printability metric of the first pattern; adjusting the design of the second pattern to reduce at least one printing error in the first pattern, wherein a functionality of the second pattern in the IC design layout is unchanged after the adjusting; and implementing OPC on the IC design layout including the target region with the adjusted second pattern therein.