公开(公告)号：US09953873B2

公开(公告)日：2018-04-24

申请号：US15163313

申请日：2016-05-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bhupesh Chandra ,  Claude Ortolland ,  Gregory G. Freeman ,  Viorel Ontalus ,  Christopher D. Sheraw ,  Timothy J. McArdle ,  Paul Chang

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/32 ,  H01L27/088

CPC classification number: H01L21/823418 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02299 ,  H01L21/32 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/088 ,  H01L29/6656

Abstract: Chip structures and fabrication methods for forming such chip structures. A first device structure has a structural feature comprised of a first dielectric material and a second device structure has a structural feature comprised of a second dielectric material. A semiconductor layer has a first section adjacent to the structural feature of the first device structure and a second section adjacent to the structural feature of the second device structure. The first section of the semiconductor layer has a popped relationship relative to the structural feature comprised of the first dielectric material. The second section of the semiconductor layer includes a portion that has a pinned relationship relative to a portion of the structural feature comprised of the second dielectric material.

公开(公告)号：US09722045B2

公开(公告)日：2017-08-01

申请号：US14921434

申请日：2015-10-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bhupesh Chandra ,  Viorel Ontalus ,  Timothy J. McArdle ,  Paul Chang ,  Claude Ortolland ,  Judson R. Holt

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/225

CPC classification number: H01L29/66575 ,  H01L21/2254 ,  H01L21/2257 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848 ,  H01L29/785

Abstract: The disclosure relates to semiconductor structures and, more particularly, to one or more devices with an engineered layer for modulating voltage threshold (Vt) and methods of manufacture. The method includes finding correlation of thickness of a buffer layer to out-diffusion of dopant into extension regions during annealing of a doped layer formed on the buffer layer. The method further includes determining a predetermined thickness of the buffer layer to adjust device performance characteristics based on the correlation of thickness of the buffer layer to the out-diffusion. The method further includes forming the buffer layer adjacent to gate structures to the predetermined thickness.

公开(公告)号：US20170345719A1

公开(公告)日：2017-11-30

申请号：US15163313

申请日：2016-05-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bhupesh Chandra ,  Claude Ortolland ,  Gregory G. Freeman ,  Viorel Ontalus ,  Christopher D. Sheraw ,  Timothy J. McArdle ,  Paul Chang

IPC: H01L21/8234 ,  H01L21/32 ,  H01L21/02 ,  H01L27/088

CPC classification number: H01L21/823418 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02299 ,  H01L21/32 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/088 ,  H01L29/6656

Abstract: Chip structures and fabrication methods for forming such chip structures. A first device structure has a structural feature comprised of a first dielectric material and a second device structure has a structural feature comprised of a second dielectric material. A semiconductor layer has a first section adjacent to the structural feature of the first device structure and a second section adjacent to the structural feature of the second device structure. The first section of the semiconductor layer has a popped relationship relative to the structural feature comprised of the first dielectric material. The second section of the semiconductor layer includes a portion that has a pinned relationship relative to a portion of the structural feature comprised of the second dielectric material.

公开(公告)号：US20180375494A1

公开(公告)日：2018-12-27

申请号：US15634397

申请日：2017-06-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vincent J. McGahay ,  Bhupesh Chandra

IPC: H03H9/56 ,  H01L41/18 ,  H01L41/257

CPC classification number: H03H9/56 ,  H01L41/18 ,  H01L41/257 ,  H03H3/02 ,  H03H3/08 ,  H03H9/02015 ,  H03H9/02543

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to artificially oriented piezoelectric films for integrated filters and methods of manufacture. The structure includes: a piezoelectric film with effective crystalline orientations of the polar axis rotated 90 degrees from a natural orientation for planar deposited films; and a conductor pattern formed on a surface of the piezoelectric film.

公开(公告)号：US10483943B2

公开(公告)日：2019-11-19

申请号：US15634397

申请日：2017-06-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vincent J. McGahay ,  Bhupesh Chandra

IPC: H03H9/56 ,  H01L41/18 ,  H03H3/08 ,  H01L41/257 ,  H03H3/02 ,  H03H9/02

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to artificially oriented piezoelectric films for integrated filters and methods of manufacture. The structure includes: a piezoelectric film with effective crystalline orientations of the polar axis rotated 90 degrees from a natural orientation for planar deposited films; and a conductor pattern formed on a surface of the piezoelectric film.

公开(公告)号：US20200036363A1

公开(公告)日：2020-01-30

申请号：US16591144

申请日：2019-10-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vincent J. McGahay ,  Bhupesh Chandra

IPC: H03H9/56 ,  H03H3/02 ,  H03H9/02 ,  H03H3/08 ,  H01L41/18 ,  H01L41/257

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to artificially oriented piezoelectric films for integrated filters and methods of manufacture. The structure includes: a piezoelectric film with effective crystalline orientations of the polar axis rotated 90 degrees from a natural orientation for planar deposited films; and a conductor pattern formed on a surface of the piezoelectric film.

公开(公告)号：US20170117387A1

公开(公告)日：2017-04-27

申请号：US14921434

申请日：2015-10-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bhupesh Chandra ,  Viorel Ontalus ,  Timothy J. McArdle ,  Paul Chang ,  Claude Ortolland ,  Judson R. Holt

IPC: H01L29/66 ,  H01L21/225

CPC classification number: H01L29/66575 ,  H01L21/2254 ,  H01L21/2257 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848 ,  H01L29/785

Abstract: The disclosure relates to semiconductor structures and, more particularly, to one or more devices with an engineered layer for modulating voltage threshold (Vt) and methods of manufacture. The method includes finding correlation of thickness of a buffer layer to out-diffusion of dopant into extension regions during annealing of a doped layer formed on the buffer layer. The method further includes determining a predetermined thickness of the buffer layer to adjust device performance characteristics based on the correlation of thickness of the buffer layer to the out-diffusion. The method further includes forming the buffer layer adjacent to gate structures to the predetermined thickness.