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公开(公告)号:US10381069B1
公开(公告)日:2019-08-13
申请号:US15891619
申请日:2018-02-08
Applicant: GLOBALFOUNDRIES INC.
Inventor: Sreenivasula Reddy Dhani Reddy , Sreejith Chidambaran , Binu Jose , Venkatraghavan Bringivijayaraghavan
IPC: G11C11/419 , G11C11/412 , G11C7/12 , G11C11/408 , H03K19/177
Abstract: A circuit includes a core having a memory array. The memory array includes memory cells and bitlines, and is arranged in columns. The core includes a metallization layer having connections to the memory array, which is devoid of memory cells. Digit lines are connected to the bitlines of a column of the memory array. A write driver is connected to the digit lines. A write assist circuit is connected to the write driver. The write assist circuit maintains a voltage on the digit lines prior to write operations and provides a boost voltage to the digit lines during write operations. A wire bridge located in the metallization layer of the core connects the write assist circuit to the write driver.
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公开(公告)号:US10600474B2
公开(公告)日:2020-03-24
申请号:US16424605
申请日:2019-05-29
Applicant: GLOBALFOUNDRIES INC.
Inventor: Sreenivasula Reddy Dhani Reddy , Sreejith Chidambaran , Binu Jose , Venkatraghavan Bringivijayaraghavan
IPC: G11C11/419 , G11C11/412 , G11C11/408 , G11C7/12 , H03K19/1776
Abstract: A circuit includes a core having a memory array. The memory array includes memory cells and bitlines, and is arranged in columns. The core includes a metallization layer having connections to the memory array, which is devoid of memory cells. Digit lines are connected to the bitlines of a column of the memory array. A write driver is connected to the digit lines. A write assist circuit is connected to the write driver. The write assist circuit maintains a voltage on the digit lines prior to write operations and provides a boost voltage to the digit lines during write operations. A wire bridge located in the metallization layer of the core connects the write assist circuit to the write driver.
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公开(公告)号:US20190279708A1
公开(公告)日:2019-09-12
申请号:US16424605
申请日:2019-05-29
Applicant: GLOBALFOUNDRIES INC.
Inventor: Sreenivasula Reddy Dhani Reddy , Sreejith Chidambaran , Binu Jose , Venkatraghavan Bringivijayaraghavan
IPC: G11C11/412 , G11C11/408 , G11C11/419 , G11C7/12
Abstract: A circuit includes a core having a memory array. The memory array includes memory cells and bitlines, and is arranged in columns. The core includes a metallization layer having connections to the memory array, which is devoid of memory cells. Digit lines are connected to the bitlines of a column of the memory array. A write driver is connected to the digit lines. A write assist circuit is connected to the write driver. The write assist circuit maintains a voltage on the digit lines prior to write operations and provides a boost voltage to the digit lines during write operations. A wire bridge located in the metallization layer of the core connects the write assist circuit to the write driver.
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公开(公告)号:US20190244658A1
公开(公告)日:2019-08-08
申请号:US15891619
申请日:2018-02-08
Applicant: GLOBALFOUNDRIES INC.
Inventor: Sreenivasula Reddy Dhani Reddy , Sreejith Chidambaran , Binu Jose , Venkatraghavan Bringivijayaraghavan
IPC: G11C11/412 , G11C11/419 , G11C11/408 , G11C7/12
CPC classification number: G11C11/412 , G11C7/12 , G11C11/4085 , G11C11/419 , H03K19/1776
Abstract: A circuit includes a core having a memory array. The memory array includes memory cells and bitlines, and is arranged in columns. The core includes a metallization layer having connections to the memory array, which is devoid of memory cells. Digit lines are connected to the bitlines of a column of the memory array. A write driver is connected to the digit lines. A write assist circuit is connected to the write driver. The write assist circuit maintains a voltage on the digit lines prior to write operations and provides a boost voltage to the digit lines during write operations. A wire bridge located in the metallization layer of the core connects the write assist circuit to the write driver.
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