公开(公告)号：US10121713B1

公开(公告)日：2018-11-06

申请号：US15589126

申请日：2017-05-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bipul C. Paul ,  Hajime Terazawa ,  Joseph Versaggi

IPC: H01L21/66 ,  H01L27/11 ,  G01R31/00 ,  G01R31/28

CPC classification number: H01L22/34 ,  G01R31/00 ,  G01R31/2856 ,  H01L22/14 ,  H01L27/1104

Abstract: Disclosed are an in-kerf test structure and testing method for testing an on-chip device. The structure includes at least one test component with at least one test device and adjoining dummy devices connected to the test device. Each adjoining dummy device has proximal node(s) directly connected to a test device and distal node(s) that are not directly connected to a test device. The nodes of each test device and the distal nodes of each adjoining dummy device are connected to input/output pads. During testing the input/output pads are used to bias the nodes of a selected test device as well as the distal node(s) of any adjoining dummy device. By biasing the distal node(s) of an adjoining dummy device, random accumulation of potential thereon is avoided and current contributions from the adjoining dummy device(s) to a current measurement taken from the selected test device can be accurately determined.