公开(公告)号：US20210020644A1

公开(公告)日：2021-01-21

申请号：US16515913

申请日：2019-07-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bipul C. Paul ,  Ruilong Xie ,  Julien Frougier ,  Daniel Chanemougame ,  Hui Zang

IPC: H01L27/11 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8238

Abstract: Methods of forming a gate cut isolation for an SRAM include forming a first and second active nanostructures adjacent to each other and separated by a space; forming a sacrificial liner over at least a side of the first active nanostructure facing the space, causing a first distance between a remaining portion of the space and the first active nanostructure to be greater than a second distance between the remaining portion of the space and the second active nanostructure. A gate cut isolation is formed in the remaining portion of the space such that it is closer to the second active nanostructure than the first active nanostructure. The sacrificial liner is removed, and gates formed over the active nanostructures with the gates separated from each other by the gate cut isolation. An SRAM including the gate cut isolation and an IC structure including the SRAM are also included.

公开(公告)号：US10685951B1

公开(公告)日：2020-06-16

申请号：US16214450

申请日：2018-12-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anuj Gupta ,  Bipul C. Paul ,  Joseph Versaggi

IPC: H01L27/02 ,  H01L27/105 ,  H01L45/00 ,  H01L21/768 ,  H01L43/12 ,  G11C5/06

Abstract: Structures for a non-volatile memory and methods for fabricating such structures. An active array region of a memory structure includes a plurality of active bitcells and a wordline. Dummy bitcells of the memory structure are arranged in a column within the active array region. An interconnect structure includes a metallization level having a wordline strap that extends across the active array region and that is arranged over the active array region.

公开(公告)号：US20200035686A1

公开(公告)日：2020-01-30

申请号：US16045920

申请日：2018-07-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bipul C. Paul ,  Ruilong Xie

IPC: H01L27/11 ,  H01L29/06 ,  G11C11/412 ,  H01L27/12

Abstract: One illustrative device disclosed herein includes a first pull-up transistor positioned in a first P-type nano-sheet and a first pull-down transistor and a first pass gate transistor positioned in a first N-type nano-sheet. The device further includes a second pull-up transistor positioned in a second P-type nano-sheet and a second pull-down transistor and a second pass gate transistor positioned in a second N-type nano-sheet. The device further inlcudes a read pull-down transistor and a read pass gate transistor positioned in a third N-type nano-sheet. The device also includes a first shared gate structure positioned adjacent the first pull-up transistor and the first pull-down transistor and a second shared gate structure positioned adjacent the second pull-up transistor, the second pull-down transistor and the read pull-down transistor.

公开(公告)号：US20190244650A1

公开(公告)日：2019-08-08

申请号：US15889369

申请日：2018-02-06

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Akhilesh Jaiswal ,  Ajey P. Jacob ,  Bipul C. Paul ,  William Taylor ,  Danny Pak-Chum Shum

IPC: G11C11/16 ,  H01L43/08 ,  H01L27/22

Abstract: A magneto-resistive memory (MRM) structure includes a source line and a first transistor that includes a source region and a drain region. The source line is electrically connected to the source region of the first transistor. The MRM structure further includes an MRM cell that includes an MRM transistor electrically in series with an MRM magnetic tunnel junction (MTJ). The MRM transistor is electrically connected to the drain region of the first transistor such that the MRM cell is electrically in series with the first transistor. Still further, the MRM structure further includes a voltage amplifier electrically connected to a mid-point node of the first transistor and the MRM transistor, a sense-amplifier electrically connected to the voltage amplifier, and a bit line electrically connected to the MRM MTJ of the MRM cell.

公开(公告)号：US10332803B1

公开(公告)日：2019-06-25

申请号：US15973817

申请日：2018-05-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Edward J. Nowak ,  Bipul C. Paul ,  Steven R. Soss ,  Julien Frougier ,  Daniel Chanemougame ,  Lars W. Liebmann

IPC: H01L21/8238 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/308 ,  H01L27/092

Abstract: Various embodiments relate to gate-all-around (GAA) transistors and methods of forming such transistors. In some embodiments, a method performed on a precursor structure includes selectively removing a sacrificial nanosheet to open a vertical gap between a pair of semiconductor nanosheets; forming a first work function metal to surround the precursor nanosheet stack and fin, the first work function metal filling the vertical gap between the pair of semiconductor nano sheets; selectively removing first work function metal surrounding the fin while preserving an entirety of first work function metal surrounding the nanosheet stack; and forming a second work function metal: over a remaining portion of the first work function metal on nanosheet stack, and surrounding the fin, where first work function metal includes a different material than second work function metal.

公开(公告)号：US10170484B1

公开(公告)日：2019-01-01

申请号：US15787009

申请日：2017-10-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Min Gyu Sung ,  Ruilong Xie ,  Bipul C. Paul

IPC: H01L21/00 ,  H01L27/11 ,  H01L29/66 ,  H01L27/088 ,  H01L29/10 ,  H01L29/417 ,  H01L29/78

Abstract: In a method of forming a structure with field effect transistors (FETs) having different drive currents, a stack is formed on a substrate. The substrate is a first semiconductor material and the stack includes alternating layers of a second and the first semiconductor material. Recess(es) filled with sacrificial material are formed in certain area(s) of the stack. The stack is patterned into fins and gate-all-around (GAA) FET processing is performed. GAAFET processing includes removing sacrificial gates to form gate openings for GAAFETs and removing the second semiconductor material and any sacrificial material (if present) from the gate openings such that, within each gate opening, nanoshape(s) that extend laterally between source/drain regions remain. Gate openings for GAAFETs where sacrificial material was removed will have fewer nanoshapes than other gate openings. Thus, in the structure, some GAAFETs will have fewer channel regions and, thereby lower drive currents than others.

公开(公告)号：US10818674B2

公开(公告)日：2020-10-27

申请号：US16295485

申请日：2019-03-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Randy W. Mann ,  Bipul C. Paul ,  Julien Frougier ,  Ruilong Xie

IPC: H01L27/11 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L27/092

Abstract: Structures and static random access memory bit cells including complementary field effect transistors and methods of forming such structures and bit cells. A first complementary field-effect transistor has a first storage nanosheet transistor, a second storage nanosheet transistor stacked over the first storage nanosheet transistor, and a first gate electrode shared by the first storage nanosheet transistor and the second storage nanosheet transistor. A second complementary field-effect transistor has a third storage nanosheet transistor, a fourth storage nanosheet transistor stacked over the third storage nanosheet transistor, and a second gate electrode shared by the third storage nanosheet transistor and the fourth storage nanosheet transistor. The first gate electrode and the second gate electrode are arranged in a spaced arrangement along a longitudinal axis. All gate electrodes of the SRAM bitcell may be arranged in a 1CPP layout.

公开(公告)号：US10756096B2

公开(公告)日：2020-08-25

申请号：US16152454

申请日：2018-10-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bipul C. Paul ,  Ruilong Xie

IPC: H01L21/84 ,  H01L27/092 ,  H01L27/11 ,  H01L23/528 ,  H01L21/768 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06

Abstract: Disclosed are structures with a complementary field effect transistor (CFET) and a buried metal interconnect that electrically connects a source/drain region of a lower-level transistor of the CFET with another device. The structure can include a memory cell with first and second CFETs, where each CFET includes a pull-up transistor stacked on and having a common gate with a pull-down transistor and each pull-down transistor has a common source/drain region with a pass-gate transistor. The metal interconnect connects a lower-level source/drain region of the first CFET (i.e., the common source/drain region of first pass-gate and pull-up transistors) to the common gate of the second CFET (i.e., to the common gate of second pull-down and pull-up transistors). Formation methods include forming an interconnect placeholder during lower-level source/drain region formation. After upper-level source/drain regions and replacement metal gates are formed, the interconnect placeholder is exposed, removed and replaced with a metal interconnect.

公开(公告)号：US10586581B1

公开(公告)日：2020-03-10

申请号：US16205921

申请日：2018-11-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Harsh N. Patel ,  Bipul C. Paul ,  Joseph Versaggi

IPC: G11C11/16 ,  G11C13/00 ,  G11C5/14 ,  H01L45/00 ,  H01L43/02 ,  H01L43/12

Abstract: Structures for a non-volatile memory and methods for forming and using such structures. A bitcell of the non-volatile memory includes a nonvolatile memory element and a field-effect transistor having a drain region coupled with the nonvolatile memory element, a source region, and a gate electrode. A word line is coupled with the gate electrode of the field-effect transistor, a bit line is coupled with the nonvolatile memory element, and a source line is coupled with the source region of the field-effect transistor. A power supply is configured to supply a negative bias voltage to the bit line in order to provide a first state for writing data to the nonvolatile memory element or to supply the negative bias voltage to the source line in order to provide a second state for writing data to the nonvolatile memory element.

公开(公告)号：US10515679B2

公开(公告)日：2019-12-24

申请号：US15889369

申请日：2018-02-06

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Akhilesh Jaiswal ,  Ajey P. Jacob ,  Bipul C. Paul ,  William Taylor ,  Danny Pak-Chum Shum

IPC: G11C11/00 ,  G11C11/16 ,  H01L27/22 ,  H01L43/08

Abstract: A magneto-resistive memory (MRM) structure includes a source line and a first transistor that includes a source region and a drain region. The source line is electrically connected to the source region of the first transistor. The MRM structure further includes an MRM cell that includes an MRM transistor electrically in series with an MRM magnetic tunnel junction (MTJ). The MRM transistor is electrically connected to the drain region of the first transistor such that the MRM cell is electrically in series with the first transistor. Still further, the MRM structure further includes a voltage amplifier electrically connected to a mid-point node of the first transistor and the MRM transistor, a sense-amplifier electrically connected to the voltage amplifier, and a bit line electrically connected to the MRM MTJ of the MRM cell.