公开(公告)号：US20180233580A1

公开(公告)日：2018-08-16

申请号：US15432710

申请日：2017-02-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong XIE ,  John H. ZHANG ,  Stan TSAI

IPC: H01L29/66 ,  H01L21/3213 ,  H01L29/423 ,  H01L21/768 ,  H01L21/311 ,  H01L29/78 ,  H01L29/417 ,  H01L29/08 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to semiconductor gate structures with gate height scaling and methods of manufacture. The method includes: forming at least one dummy gate structure with hardmask material; forming a plurality of materials over source and drain regions on sides of the at least one dummy gate structure; removing upper materials of the hardmask material such that a first material of the hardmask material remains on the dummy gate structure and in combination with a blocking material of the plurality of materials maintains a uniform gate height; forming a replacement gate structure by removing remaining material of the dummy gate structure to form a trench and depositing replacement gate material in the trench; and forming contacts to the source and drain regions.

公开(公告)号：US20170352591A1

公开(公告)日：2017-12-07

申请号：US15653127

申请日：2017-07-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： John H. ZHANG ,  Carl J. RADENS ,  Lawrence A. CLEVENGER

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76897 ,  H01L21/76808 ,  H01L21/76816

Abstract: A method for producing self-aligned line end vias and the resulting device are provided. Embodiments include trench lines formed in a dielectric layer; each trench line including a pair of self aligned line end vias; and a high-density plasma (HDP) oxide, silicon carbide (SiC) or silicon carbon nitride (SiCNH) formed between each pair of self aligned line end vias, wherein the trench lines and self aligned line end vias are filled with a metal liner and metal.