公开(公告)号：US20190094294A1

公开(公告)日：2019-03-28

申请号：US15801380

申请日：2017-11-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sukeshwar Kannan ,  Abhishek Koneru ,  Krishnendu Chakrabarty

IPC: G01R31/28 ,  G01R31/27 ,  G01R31/319

Abstract: Monolithic three-dimensional integration can achieve higher device density compared to 3D integration using through-silicon vias. A test solution for M3D integrated circuits (ICs) is based on dedicated test layers inserted between functional layers. A structure includes a first functional layer having first functional components of the IC with first test scan chains and a second functional layer having second functional components of the IC with second test scan chains. A dedicated test layer is located between the first functional layer and the second functional layer. The test layer includes an interface register controlling signals from a testing module to one of the first test scan chains and the second test scan chains, and an instruction register connected to the interface register. The instruction register processes testing instructions from the testing module. Inter-layer vias connect the first functional components, the second functional components, and the testing module through the test layer.