公开(公告)号：US09269642B2

公开(公告)日：2016-02-23

申请号：US13915947

申请日：2013-06-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Michael T. Coster ,  Mark A. DiRocco ,  Jeffrey P. Gambino ,  Kirk D. Peterson

IPC: H01L21/66 ,  H01L33/62 ,  H01L23/48

CPC classification number: H01L22/14 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Aspects of the present invention relate to methods of testing an integrated circuit of a wafer and testing structures for integrated circuits. The methods include depositing a sacrificial material over a first conductor material of the integrated circuit, and contacting a test probe to the deposited sacrificial material. The methods can also include testing the integrated circuit using the test probe contacting the sacrificial material. Finally, the methods can include removing the sacrificial material over the first conductor material of the integrated circuit subsequent to the testing of the integrated circuit.

Abstract translation: 本发明的方面涉及测试晶片的集成电路和用于集成电路的测试结构的方法。 所述方法包括在集成电路的第一导体材料上沉积牺牲材料，并使测试探针与沉积的牺牲材料接触。 这些方法还可以包括使用与牺牲材料接触的测试探针来测试集成电路。 最后，该方法可以包括在集成电路的测试之后去除集成电路的第一导体材料上的牺牲材料。