公开(公告)号：US20190221483A1

公开(公告)日：2019-07-18

申请号：US15869325

申请日：2018-01-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： George MULFINGER ,  Scott BEASOR ,  Timothy MCARDLE

IPC: H01L21/8238 ,  H01L21/28

CPC classification number: H01L21/823807 ,  H01L21/28088 ,  H01L21/28255 ,  H01L21/30604 ,  H01L21/823814 ,  H01L21/823821 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/1054 ,  H01L29/42392 ,  H01L29/7853

Abstract: A method of forming nanosheet and nanowire transistors includes the formation of alternating epitaxial layers of silicon germanium (SiGe) and silicon (Si). The silicon germanium layers include etch-selective high-germanium content silicon germanium layers and low-germanium content silicon germanium layers. Single work function metal PFET and NFET devices can be formed on the same substrate by incorporating the low-germanium content silicon germanium layers into the channel region within p-type device regions, whereas both the high-germanium content silicon germanium layers and the low-germanium content silicon germanium layers are removed from within n-type device regions.