公开(公告)号：US20170338180A1

公开(公告)日：2017-11-23

申请号：US15157582

申请日：2016-05-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Scott BEASOR ,  Jagar SINGH

IPC: H01L23/525 ,  H01L27/06 ,  H01L23/522 ,  H01L21/8234 ,  H01L23/34 ,  H01L29/45 ,  H01L23/528

CPC classification number: H01L23/5256 ,  H01L21/823475 ,  H01L23/3677 ,  H01L27/0629

Abstract: A method for producing semiconductor devices including an electrical fuse (e-fuse) and the resulting device are provided. Embodiments include forming a gate electrode (PC); forming at least one gate contact (CB) over the PC; forming at least one source/drain contact (CA); and forming an e-fuse including a resistor metal (RM) between at least one CB and an equal number of CAs to dissipate heat generated by the PC.

公开(公告)号：US20180277427A1

公开(公告)日：2018-09-27

申请号：US15988145

申请日：2018-05-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Viraj SARDESAI ,  Suraj K. PATIL ,  Scott BEASOR ,  Vimal Kumar KAMINENI

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/76849 ,  H01L21/76802 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76886 ,  H01L21/76889 ,  H01L23/5226 ,  H01L23/53209

Abstract: A process for forming a conductive structure includes the formation of a self-aligned silicide cap over a cobalt-based contact. The silicide cap is formed in situ by the deposition of a thin silicon layer over exposed portions of a cobalt contact, followed by heat treatment to react the deposited silicon with the cobalt and form cobalt silicide, which is an effective barrier to cobalt migration and oxidation.

公开(公告)号：US20150311293A1

公开(公告)日：2015-10-29

申请号：US14259726

申请日：2014-04-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shiv Kumar MISHRA ,  Zhiqing LI ,  Scott BEASOR ,  Shesh Mani PANDEY

IPC: H01L29/36 ,  H01L29/66 ,  H01L21/02 ,  H01L29/16 ,  H01L29/78

CPC classification number: H01L29/365 ,  H01L21/02532 ,  H01L21/02579 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/66477 ,  H01L29/66568 ,  H01L29/78

Abstract: P-type metal-oxide semiconductor field-effect transistors (pMOSFET's), semiconductor devices comprising the pMOSFET's, and methods of forming pMOSFET's are provided. The pMOSFET's include a silicon-germanium (SiGe) film that has a lower interface in contact with a semiconductor substrate and an upper surface, and the SiGe film has a graded boron doping profile where boron content increases upwardly over a majority of the width of boron-doped SiGe film between the lower interface of the SiGe film and the upper surface of the SiGe film. Methods of forming the pMOSFET's include: providing a semiconductor substrate; depositing a SiGe film on the semiconductor substrate, thereby forming a lower interface of the SiGe film in contact with the semiconductor substrate, and an upper surface of the SiGe film; and doping the SiGe film with boron to form a SiGe film having a graded boron doping profile where boron content increases upwardly over a majority of the width of boron-doped SiGe film between the lower interface of the SiGe film and the upper surface of the SiGe film.

Abstract translation: 提供了P型金属氧化物半导体场效应晶体管（pMOSFET），包括pMOSFET的半导体器件和形成pMOSFET的方法。 pMOSFET包括具有与半导体衬底和上表面接触的较低界面的硅 - 锗（SiGe）膜，并且SiGe膜具有梯度硼掺杂分布，其中硼含量在硼的宽度的大部分上向上增加 SiGe膜的下界面与SiGe膜的上表面之间的掺杂SiGe膜。 形成pMOSFET的方法包括：提供半导体衬底; 在半导体衬底上沉积SiGe膜，从而形成与半导体衬底接触的SiGe膜的下界面和SiGe膜的上表面; 并且用硼掺杂SiGe膜以形成具有渐变硼掺杂分布的SiGe膜，其中硼含量在SiGe膜的下界面和SiGe的上表面之间的硼掺杂SiGe膜的宽度的大部分上向上增加 电影。

公开(公告)号：US20180233505A1

公开(公告)日：2018-08-16

申请号：US15719014

申请日：2017-09-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George R. MULFINGER ,  Lakshmanan H. VANAMURTHY ,  Scott BEASOR ,  Timothy J. MCARDLE ,  Judson R. HOLT ,  Hao ZHANG

IPC: H01L27/092 ,  H01L29/08 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/165 ,  H01L21/02 ,  H01L29/167 ,  H01L21/285 ,  H01L29/66 ,  H01L21/265 ,  H01L29/45

Abstract: A method for forming a self-aligned sacrificial epitaxial cap for trench silicide and the resulting device are provided. Embodiments include a Si fin formed in a PFET region; a pair of Si fins formed in a NFET region; epitaxial S/D regions formed on ends of the Si fins; a replacement metal gate formed over the Si fins in the PFET and NFET regions; metal silicide trenches formed over the epitaxial S/D regions in the PFET and NEFT regions; a metal layer formed over top surfaces of the S/D region in the PFET region and top and bottom surfaces of the S/D regions in the NFET region, wherein the epitaxial S/D regions in the PFET and NFET regions are diamond shaped in cross-sectional view.

公开(公告)号：US20180096899A1

公开(公告)日：2018-04-05

申请号：US15285978

申请日：2016-10-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Scott BEASOR ,  Jeremy A. WAHL

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823821 ,  H01L21/823807 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66553 ,  H01L29/6681 ,  H01L29/7851 ,  H01L29/7853

Abstract: A method for integrating nanostructures in finFET processing and a related device are provided. Embodiments include forming fins in a Si substrate in first and second device regions; forming STI regions in spaces between fins; forming a first hardmask over the fins and STI regions; removing a portion of the first hardmask over the first device region to expose upper surfaces of the fins and STI regions in the first device region; recessing an upper portion of the fins; forming first devices over the recessed fins; forming a second hardmask over the fins and STI regions; removing a portion of the second hardmask over the second device region to expose upper surfaces of the fins and STI regions; recessing an upper portion of the fins; and forming second devices, different from the first devices, over the recessed fins, wherein the first and/or second devices include nanowire or nanosheet devices.

公开(公告)号：US20190378763A1

公开(公告)日：2019-12-12

申请号：US16005073

申请日：2018-06-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting WANG ,  Ruilong XIE ,  Shesh Mani PANDEY ,  Hui ZANG ,  Garo Jacques DERDERIAN ,  Scott BEASOR

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L21/308 ,  H01L21/762 ,  H01L27/02

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a hybrid fin cut with improved fin profiles and methods of manufacture. The structure includes: a plurality of fin structures in a first region of a first density of fin structures; a plurality of fin structures in a second region of a second density of fin structures; and a plurality of fin structures in a third region of a third density of fin structures. The first density, second density and third density of fin structures are different densities of fin structures, and the plurality of fin structures in the first region, the second region and the third region have a substantially uniform profile.

公开(公告)号：US20190355838A1

公开(公告)日：2019-11-21

申请号：US15980436

申请日：2018-05-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Ruilong XIE ,  Scott BEASOR

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L21/768 ,  H01L21/28

Abstract: A method for producing a finFET to prevent gate contact and trench silicide (TS) electrical shorts. Embodiments include forming a finFET over a substrate, the finFET comprising an epi S/D region formed at sides of a gate; forming an α-Si layer in a recess over the epi S/D; forming an oxide layer over the α-Si layer; forming a non-TS isolation opening over the substrate; forming a low dielectric constant layer in the non-TS isolation opening; removing the oxide layer and α-Si layer; forming an opening over the gate and an opening over the epi S/D region; and forming a gate contact in the opening over the gate and an epi S/D contact over the opening over the epi S/D region.

公开(公告)号：US20180130703A1

公开(公告)日：2018-05-10

申请号：US15347119

申请日：2016-11-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Viraj SARDESAI ,  Suraj K. PATIL ,  Scott BEASOR ,  Vimal Kumar KAMINENI

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76849 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76886 ,  H01L23/5226 ,  H01L23/53209

Abstract: A process for forming a conductive structure includes the formation of a self-aligned silicide cap over a cobalt-based contact. The silicide cap is formed in situ by the deposition of a thin silicon layer over exposed portions of a cobalt contact, followed by heat treatment to react the deposited silicon with the cobalt and form cobalt silicide, which is an effective barrier to cobalt migration and oxidation.

公开(公告)号：US20190221483A1

公开(公告)日：2019-07-18

申请号：US15869325

申请日：2018-01-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： George MULFINGER ,  Scott BEASOR ,  Timothy MCARDLE

IPC: H01L21/8238 ,  H01L21/28

CPC classification number: H01L21/823807 ,  H01L21/28088 ,  H01L21/28255 ,  H01L21/30604 ,  H01L21/823814 ,  H01L21/823821 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/1054 ,  H01L29/42392 ,  H01L29/7853

Abstract: A method of forming nanosheet and nanowire transistors includes the formation of alternating epitaxial layers of silicon germanium (SiGe) and silicon (Si). The silicon germanium layers include etch-selective high-germanium content silicon germanium layers and low-germanium content silicon germanium layers. Single work function metal PFET and NFET devices can be formed on the same substrate by incorporating the low-germanium content silicon germanium layers into the channel region within p-type device regions, whereas both the high-germanium content silicon germanium layers and the low-germanium content silicon germanium layers are removed from within n-type device regions.

公开(公告)号：US20190164898A1

公开(公告)日：2019-05-30

申请号：US15823899

申请日：2017-11-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui ZANG ,  Guowei XU ,  Scott BEASOR ,  Ruilong Xie

IPC: H01L23/532 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L21/311

Abstract: In the manufacture of a FinFET device, an isolation architecture is provided between gate and source/drain contact locations. The isolation architecture may include a low-k spacer layer and a contact etch stop layer. An upper portion of the isolation architecture is removed and replaced with a high-k, etch-selective spacer layer adapted to resist degradation during an etch to open the source/drain contact locations. The high-k spacer layer, in conjunction with a self-aligned contact (SAC) capping layer disposed over the gate and overlapping a sidewall of the isolation layer, forms an improved isolation structure that inhibits short circuits or parasitic capacitance between the gate and source/drain contacts.