公开(公告)号：US10217839B2

公开(公告)日：2019-02-26

申请号：US15468170

申请日：2017-03-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chanro Park ,  Kisup Chung ,  Victor Chan ,  Koji Watanabe

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/49 ,  H01L29/417 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/28

Abstract: Disclosed is a field effect transistor (FET) with a replacement metal gate (RMG) and a method of forming the FET. The RMG includes a conformal gate dielectric layer and a stack of gate conductor layers on the gate dielectric layer. The stack includes a conformal work function metal (WFM) layer and a conductive fill material (CFM) layer on the WFM layer. Within the stack, the top surface of the CFM layer is above the level of the top of an adjacent vertical portion of the WFM layer. A dielectric gate cap has a center portion and an edge portion. The center portion is above the top surface of the CFM layer and the edge portion is above the top of the adjacent vertical portion of the WFM layer and is further positioned laterally immediately adjacent to an upper portion of an outer sidewall of the CFM layer.

公开(公告)号：US20180277652A1

公开(公告)日：2018-09-27

申请号：US15468170

申请日：2017-03-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chanro Park ,  Kisup Chung ,  Victor Chan ,  Koji Watanabe

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L29/417 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/76897 ,  H01L29/41775 ,  H01L29/42376 ,  H01L29/4958 ,  H01L29/4966

Abstract: A hash table method and structure comprises a processor that receives a plurality of access requests for access to a storage device. The processor performs a plurality of hash processes on the access requests to generate a first number of addresses for each access request. Such addresses are within a full address range. Hash table banks are operatively connected to the processor. The hash table banks form the storage device. Each of the hash table banks has a plurality of input ports. Specifically, each of the hash table banks has less input ports than the first number of addresses for each access request. The processor provides the addresses to the hash table banks, and each of the hash table banks stores pointers corresponding to a different limited range of addresses within the full address range (each of the different limited range of addresses is less than the full address range).