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    Method for growing strain-inducing materials in CMOS circuits in a gate first flow
    3.
    发明授权
    Method for growing strain-inducing materials in CMOS circuits in a gate first flow 有权
    在栅极第一流中在CMOS电路中增长应变诱导材料的方法

    公开(公告)号：US08779525B2

    公开(公告)日：2014-07-15

    申请号：US13772401

    申请日：2013-02-21

    Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

    Inventor： Bo Bai ,  Linda Black ,  Abhishek Dube ,  Judson R. Holt ,  Viorel C. Ontalus ,  Kathryn T. Schonenberg ,  Matthew W. Stoker ,  Keith H. Tabakman

    IPC: H01L21/8238

    CPC classification number: H01L21/823807 ,  H01L21/823828

    Abstract: A complementary metal oxide semiconductor (CMOS) circuit incorporating a substrate and a gate wire over the substrate. The substrate comprises an n-type field effect transistor (n-FET) region, a p-type field effect transistor (p-FET) region and an isolation region disposed between the n-FET and p-FET regions. The gate wire comprises an n-FET gate, a p-FET gate, and gate material extending transversely from the n-FET gate across the isolation region to the p-FET gate. A first conformal insulator covers the gate wire and a second conformal insulator is on the first conformal insulator positioned over the p-FET gate without extending laterally over the n-FET gate. Straining regions for producing different types of strain are formed in recess etched into the n-FET and p-FET regions of the substrate.

    Abstract translation: 在衬底上并入衬底和栅极线的互补金属氧化物半导体（CMOS）电路。 衬底包括n型场效应晶体管（n-FET）区域，p型场效应晶体管（p-FET）区域和设置在n-FET和p-FET区域之间的隔离区域。 栅极线包括n-FET栅极，p-FET栅极和从跨越隔离区域的n-FET栅极横向延伸到p-FET栅极的栅极材料。 第一共形绝缘体覆盖栅极线，并且第二共形绝缘体位于位于p-FET栅极上方的第一共形绝缘体上，而不横向延伸穿过n-FET栅极。 用于产生不同类型应变的应变区形成在蚀刻到衬底的n-FET和p-FET区中的凹槽中。

    METHOD FOR GROWING STRAIN-INDUCING MATERIALS IN CMOS CIRCUITS IN A GATE FIRST FLOW
    4.
    发明申请
    METHOD FOR GROWING STRAIN-INDUCING MATERIALS IN CMOS CIRCUITS IN A GATE FIRST FLOW 有权
    在门电路第一流程中生长应变诱导材料的方法

    公开(公告)号：US20130161759A1

    公开(公告)日：2013-06-27

    申请号：US13772401

    申请日：2013-02-21

    Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

    Inventor： Bo Bai ,  Linda Black ,  Abhishek Dube ,  Judson R. Holt ,  Viorel C. Ontalus ,  Kathryn T. Schonenberg ,  Matthew W. Stoker ,  Keith H. Tabakman

    IPC: H01L27/092

    CPC classification number: H01L21/823807 ,  H01L21/823828

    Abstract: A complementary metal oxide semiconductor (CMOS) circuit incorporating a substrate and a gate wire over the substrate. The substrate comprises an n-type field effect transistor (n-FET) region, a p-type field effect transistor (p-FET) region and an isolation region disposed between the n-FET and p-FET regions. The gate wire comprises an n-FET gate, a p-FET gate, and gate material extending transversely from the n-FET gate across the isolation region to the p-FET gate. A first conformal insulator covers the gate wire and a second conformal insulator is on the first conformal insulator positioned over the p-FET gate without extending laterally over the n-FET gate. Straining regions for producing different types of strain are formed in recess etched into the n-FET and p-FET regions of the substrate.

    Abstract translation: 在衬底上并入衬底和栅极线的互补金属氧化物半导体（CMOS）电路。 衬底包括n型场效应晶体管（n-FET）区域，p型场效应晶体管（p-FET）区域和设置在n-FET和p-FET区域之间的隔离区域。 栅极线包括n-FET栅极，p-FET栅极和从跨越隔离区域的n-FET栅极横向延伸到p-FET栅极的栅极材料。 第一共形绝缘体覆盖栅极线，并且第二共形绝缘体位于位于p-FET栅极上方的第一共形绝缘体上，而不横向延伸穿过n-FET栅极。 用于产生不同类型应变的应变区形成在蚀刻到衬底的n-FET和p-FET区中的凹槽中。

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