公开(公告)号：US09349650B2

公开(公告)日：2016-05-24

申请号：US14524246

申请日：2014-10-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kevin K. Chan ,  Yue Ke ,  Annie Levesque ,  Dae-Gyu Park ,  Ravikumar Ramachandran ,  Amanda L. Tessier ,  Min Yang

IPC: H01L21/8234 ,  H01L29/78 ,  H01L21/02 ,  H01L21/285 ,  H01L29/66 ,  H01L21/223 ,  H01L21/265 ,  H01L27/088 ,  H01L29/08

CPC classification number: H01L21/823431 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/223 ,  H01L21/2236 ,  H01L21/26566 ,  H01L21/28518 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/7853

Abstract: A gate structure is formed straddling a first portion of a plurality of semiconductor fins that extend upwards from a topmost surface of an insulator layer. A dielectric spacer is formed on sidewalls of the gate structure and straddling a second portion of the plurality of semiconductor fins. Epitaxial semiconductor material portions that include a non-planar bottommost surface and a non-planar topmost surface are grown from at least the exposed sidewalls of each semiconductor fin not including the gate structure or the gate spacer to merge adjacent semiconductor fins. A gap is present beneath epitaxial semiconductor material portions and the topmost surface of the insulator layer. A second epitaxial semiconductor material is formed on the epitaxial semiconductor material portions and thereafter the second epitaxial semiconductor material is converted into a metal semiconductor alloy.

Abstract translation: 栅极结构跨越从绝缘体层的最上表面向上延伸的多个半导体鳍片的第一部分形成。 介电隔离件形成在栅极结构的侧壁上并且跨越多个半导体鳍片的第二部分。 至少从不包括栅极结构或栅极间隔物的半导体鳍片的暴露的侧壁至少生长包括非平面最底表面和非平面最上表面的外延半导体材料部分，以使相邻的半导体鳍片合流。 在外延半导体材料部分和绝缘体层的最上表面之下存在间隙。 在外延半导体材料部分上形成第二外延半导体材料，然后将第二外延半导体材料转换成金属半导体合金。

公开(公告)号：US10886178B2

公开(公告)日：2021-01-05

申请号：US16109258

申请日：2018-08-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tek Po Rinus Lee ,  Annie Levesque ,  Qun Gao ,  Hui Zang ,  Rishikesh Krishnan ,  Bharat Krishnan ,  Curtis Durfee

IPC: H01L29/167 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L23/532 ,  H01L21/02 ,  H01L29/40 ,  H01L23/535

Abstract: A device including a triple-layer EPI stack including SiGe, Ge, and Si, respectively, with Ga confined therein, and method of production thereof. Embodiments include an EPI stack including a SiGe layer, a Ge layer, and a Si layer over a plurality of fins, the EPI stack positioned between and over a portion of sidewall spacers, wherein the Si layer is a top layer capping the Ge layer, and wherein the Ge layer is a middle layer capping the SiGe layer underneath; and a Ga layer in a portion of the Ge layer between the SiGe layer and the Si layer.

公开(公告)号：US09673295B2

公开(公告)日：2017-06-06

申请号：US14287506

申请日：2014-05-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Annie Levesque ,  Viorel C. Ontalus ,  Matthew W. Stoker

IPC: H01L29/66 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/78 ,  H01L21/285 ,  H01L29/165

CPC classification number: H01L29/665 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: A transistor contact structure and methods of making the same. The method includes forming a first semiconductor layer in a source/drain opening of a substrate, the first layer having a non-planar top surface; forming a second semiconductor layer directly on the first layer, the second layer having a defect density greater than the first layer; and forming a silicide region formed with the second layer, the silicide region having a non-planar interface with the first layer. A portion of the silicide interface may be higher than a top surface of the substrate and another portion may be below.

公开(公告)号：US09349649B2

公开(公告)日：2016-05-24

申请号：US14315844

申请日：2014-06-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kevin K. Chan ,  Yue Ke ,  Annie Levesque ,  Dae-Gyu Park ,  Ravikumar Ramachandran ,  Amanda L. Tessier ,  Min Yang

IPC: H01L21/8234 ,  H01L29/78 ,  H01L21/02 ,  H01L21/285 ,  H01L29/66 ,  H01L21/223 ,  H01L21/265 ,  H01L27/088 ,  H01L29/08 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L21/823431 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/223 ,  H01L21/2236 ,  H01L21/26566 ,  H01L21/28518 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/7853

Abstract: A gate structure is formed straddling a first portion of a plurality of semiconductor fins that extend upwards from a topmost surface of an insulator layer. A dielectric spacer is formed on sidewalls of the gate structure and straddling a second portion of the plurality of semiconductor fins. Epitaxial semiconductor material portions that include a non-planar bottommost surface and a non-planar topmost surface are grown from at least the exposed sidewalls of each semiconductor fin not including the gate structure or the gate spacer to merge adjacent semiconductor fins. A gap is present beneath epitaxial semiconductor material portions and the topmost surface of the insulator layer. A second epitaxial semiconductor material is formed on the epitaxial semiconductor material portions and thereafter the second epitaxial semiconductor material is converted into a metal semiconductor alloy.