公开(公告)号：US10197730B1

公开(公告)日：2019-02-05

申请号：US15806931

申请日：2017-11-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yves T. Ngu ,  Vibhor Jain ,  John J. Ellis-Monaghan ,  Sebastian Theodore Ventrone ,  Saurabh Sirohi

IPC: G02B6/12 ,  G02B6/293 ,  G02F1/01 ,  G02F1/025

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to optical via connections in chip-to-chip transmission in a 3D chip stack structure using an optical via, and methods of manufacture. The structure has a first wafer, including a first waveguide coupled to an optical resonator in the first wafer, and a second wafer, including a second waveguide, located over the first wafer. The structure also includes an optical via extending between the optical resonator of the first wafer and the second waveguide of the second wafer to optically couple the first and second waveguides.

公开(公告)号：US09412736B2

公开(公告)日：2016-08-09

申请号：US14296812

申请日：2014-06-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yan Ding ,  Vibhor Jain ,  Thomas Kessler ,  Yves T. Ngu ,  Robert M. Rassel ,  Sebastian T. Ventrone

IPC: H01L21/30 ,  H01L27/06 ,  H01L23/48 ,  H01L21/768 ,  H01L23/367 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L27/0694 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/3677 ,  H01L23/481 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In an approach to fabricating a silicon on insulator wafer, one or more semiconductor device elements are implanted and one or more shallow trench isolations are formed on a top surface of a first semiconductor wafer. A first dielectric material layer is deposited over the top surface of the first semiconductor wafer, filling the shallow trench isolations. A dielectric material layer on a bottom surface of a second semiconductor wafer is bonded to a dielectric material layer on the top of the first semiconductor wafer and one or more semiconductor devices are formed on a top surface of the second semiconductor wafer. Then, one or more through silicon vias are created connecting the one or more semiconductor devices on the top surface of the second semiconductor wafer and the one or more semiconductor device elements on the top surface of the first semiconductor wafer.

Abstract translation: 在制造绝缘体上硅晶片的方法中，注入一个或多个半导体器件元件，并且在第一半导体晶片的顶表面上形成一个或多个浅沟槽隔离。 在第一半导体晶片的顶表面上沉积第一介电材料层，填充浅沟槽隔离物。 在第二半导体晶片的底面上的电介质材料层与第一半导体晶片的顶部的电介质材料层接合，在第二半导体晶片的顶面上形成有一个以上的半导体装置。 然后，产生连接第二半导体晶片的顶表面上的一个或多个半导体器件和第一半导体晶片的顶表面上的一个或多个半导体器件元件的一个或多个穿过硅通孔。