公开(公告)号：US09477550B2

公开(公告)日：2016-10-25

申请号：US14062856

申请日：2013-10-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Benjiman L. Goodman ,  Luis A. Lastras-Montano ,  Eric E. Retter ,  Kenneth L. Wright

IPC: G11C8/06 ,  G11C29/44 ,  G11C29/42 ,  G11C29/04 ,  G06F11/10

CPC classification number: G06F11/1076 ,  G06F11/10 ,  G06F11/1012 ,  G06F11/1048 ,  G06F11/1052 ,  G11C8/06 ,  G11C29/42 ,  G11C29/44 ,  G11C2029/0411

Abstract: A memory controller is equipped with multiple error correction circuits for different complexity levels of errors, but requested data is initially sent to a requesting unit (e.g., processor) via a bypass path which provides the lowest memory latency. The requesting unit performs error detection and, if an error is found, sends a retry select signal to the memory controller. The retry select signal provides an indication of which error correction unit should be used to provide complete correction of the error but add the minimum latency necessary. On the retry transmission, the controller uses the particular error correction unit indicated by the retry select signal. The memory controller can also have a persistent error detection circuit which identifies an address as being defective when an error is repeatedly indicated by multiple retry select signals, and the control logic can automatically transmits the requested data using the appropriate error correction unit.

公开(公告)号：US09436548B2

公开(公告)日：2016-09-06

申请号：US14098561

申请日：2013-12-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Benjiman L. Goodman ,  Luis A. Lastras-Montano ,  Eric E. Retter ,  Kenneth L. Wright

IPC: G11C29/00 ,  G06F11/10 ,  G11C29/44 ,  G11C29/04 ,  G11C29/42 ,  G11C8/06

CPC classification number: G06F11/1076 ,  G06F11/10 ,  G06F11/1012 ,  G06F11/1048 ,  G06F11/1052 ,  G11C8/06 ,  G11C29/42 ,  G11C29/44 ,  G11C2029/0411

Abstract: A memory controller is equipped with multiple error correction circuits for different complexity levels of errors, but requested data is initially sent to a requesting unit (e.g., processor) via a bypass path which provides the lowest memory latency. The requesting unit performs error detection and, if an error is found, sends a retry select signal to the memory controller. The retry select signal provides an indication of which error correction unit should be used to provide complete correction of the error but add the minimum latency necessary. On the retry transmission, the controller uses the particular error correction unit indicated by the retry select signal. The memory controller can also have a persistent error detection circuit which identifies an address as being defective when an error is repeatedly indicated by multiple retry select signals, and the control logic can automatically transmits the requested data using the appropriate error correction unit.

Abstract translation: 存储器控制器配备有用于不同复杂度错误水平的多个纠错电路，但是请求的数据最初经由提供最低存储器延迟的旁路路径发送到请求单元（例如，处理器）。 请求单元执行错误检测，并且如果发现错误，则将重试选择信号发送到存储器控制器。 重试选择信号提供了哪个错误校正单元应该用于提供错误的完整校正的指示，但是添加最小等待时间。 在重试传输中，控制器使用由重试选择信号指示的特定纠错单元。 存储器控制器还可以具有持续错误检测电路，其在由多个重试选择信号重复指示错误时将地址标识为有缺陷，并且控制逻辑可以使用适当的纠错单元自动发送所请求的数据。

公开(公告)号：US09355035B2

公开(公告)日：2016-05-31

申请号：US14082199

申请日：2013-11-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Benjiman L. Goodman ,  Jody B. Joyner ,  Stephen J. Powell ,  William J. Starke ,  Jeffrey A. Stuecheli

IPC: G06F12/00 ,  G06F12/08

CPC classification number: G06F12/0828 ,  G06F12/0864 ,  G06F2212/621 ,  Y02D10/13

Abstract: A set associative cache is managed by a memory controller which places writeback instructions for modified (dirty) cache lines into a virtual write queue, determines when the number of the sets containing a modified cache line is greater than a high water mark, and elevates a priority of the writeback instructions over read operations. The controller can return the priority to normal when the number of modified sets is less than a low water mark. In an embodiment wherein the system memory device includes rank groups, the congruence classes can be mapped based on the rank groups. The number of writes pending in a rank group exceeding a different threshold can additionally be a requirement to trigger elevation of writeback priority. A dirty vector can be used to provide an indication that corresponding sets contain a modified cache line, particularly in least-recently used segments of the corresponding sets.

Abstract translation: 集合关联缓存由存储器控制器管理，存储器控制器将修改（脏）高速缓存行的回写指令放入虚拟写入队列中，确定包含修改的高速缓存行的集合的数量何时大于高水位标记，并且升高一个 回读指令优先于读取操作。 当修改集合的数量小于低水位时，控制器可以将优先级恢复为正常。 在其中系统存储器件包括等级组的实施例中，可以基于等级组映射一致等级。 超过不同阈值的等级组中挂起的写入次数还可以是触发提高回写优先级的要求。 可以使用脏向量来提供对应集合包含修改的高速缓存行的指示，特别是相应集合的最近最少使用的段。