公开(公告)号：US09425129B1

公开(公告)日：2016-08-23

申请号：US14789160

申请日：2015-07-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Bingwu Liu ,  Dingyou Zhang

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/528 ,  H01L29/16 ,  H01L29/161 ,  H01L21/02

CPC classification number: H01L23/481 ,  H01L21/76831 ,  H01L21/76898 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165

Abstract: Methods and structures for fabricating conductive vias in circuit structures are provided. Methods may include, for example, providing a substrate that includes a dopant and at least one trench formed in the substrate; providing an undoped semiconductor layer over a surface of the substrate within the trench; and providing a conductive material on top of dielectric layer in the trench, the conductive material forming the conductive via. The undoped semiconductor layer, having no dopant, reduces a parasitic capacitance between the conductive via and the substrate. The undoped semiconductor layer may also prevent migration of dopant from the substrate into the undoped semiconductor layer, further reducing capacitance in the circuit structure.

Abstract translation: 提供了在电路结构中制造导电通孔的方法和结构。 方法可以包括例如提供包括掺杂剂的衬底和在衬底中形成的至少一个沟槽; 在所述沟槽内的所述衬底的表面上提供未掺杂的半导体层; 并且在沟槽中的电介质层的顶部提供导电材料，导电材料形成导电通孔。 没有掺杂剂的未掺杂的半导体层降低了导电通孔和衬底之间的寄生电容。 未掺杂的半导体层还可以防止掺杂剂从衬底迁移到未掺杂的半导体层中，进一步降低电路结构中的电容。