公开(公告)号：US10096488B2

公开(公告)日：2018-10-09

申请号：US15608283

申请日：2017-05-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Michael Ganz ,  Bingwu Liu ,  Johannes Marinus Van Meer ,  Sruthi Muralidharan

IPC: H01L21/02 ,  H01L21/266 ,  H01L29/78 ,  H01L21/324 ,  H01L21/3213 ,  H01L29/66 ,  H01L21/265 ,  H01L21/268 ,  H01L21/3105

Abstract: The invention provides a method of forming a semiconductor structure, which include: providing an intermediate semiconductor structure having semiconductor substrate, a fin having an EG oxide layer in contact with at least a portion of the fin, and a gate stack disposed over a portion of the fin; forming a silicon nitride layer over portions of the fin that are not located under the gate stack; and after forming the silicon nitride layer, performing one or more ion implantation steps on the intermediate semiconductor structure. The invention also provides a method of forming a semiconductor structure including: providing an intermediate semiconductor structure having a semiconductor substrate, a fin having an EG oxide layer in contact with at least a portion of the fin, and a gate material disposed over the fin; forming, over the fin and gate material of the intermediate semiconductor structure, a gate stack hardmask including an oxide layer; forming a silicon nitride barrier layer on the oxide layer of the gate stack hardmask; performing one or more gate stack hardmask patterning steps; removing the EG oxide layer from portions of the fin that are not located under the gate; and subsequent to removing the EG oxide layer from portions of the fin that are not located under the gate, performing one or more ion implantation steps.

公开(公告)号：US09331202B2

公开(公告)日：2016-05-03

申请号：US14731876

申请日：2015-06-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bingwu Liu ,  Hui Zang

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/84 ,  H01L29/423 ,  H01L21/8234

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/66818

Abstract: One illustrative method disclosed herein includes, among other things, forming a fin protection layer around a fin, forming a sacrificial gate electrode above a section of the fin protection layer, forming at least one sidewall spacer adjacent the sacrificial gate electrode, removing the sacrificial gate electrode to define a gate cavity that exposes a portion of the fin protection layer, oxidizing at least the exposed portion of the fin protection layer to thereby form an oxidized portion of the fin protection layer, and removing the oxidized portion of the fin protection layer so as to thereby expose a surface of the fin within the gate cavity.

Abstract translation: 本文公开的一种说明性方法包括在鳍周围形成翅片保护层，在翅片保护层的一部分上形成牺牲栅电极，形成邻近牺牲栅电极的至少一个侧壁间隔物，去除牺牲栅极 电极，以限定露出所述鳍片保护层的一部分的栅极腔，至少氧化所述鳍片保护层的暴露部分，从而形成所述鳍片保护层的氧化部分，以及去除所述鳍片保护层的氧化部分，从而 从而使得在门腔内的翅片的表面露出。

公开(公告)号：US09024368B1

公开(公告)日：2015-05-05

申请号：US14079757

申请日：2013-11-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  Hyucksoo Yang ,  Bingwu Liu ,  Puneet Khanna ,  Lun Zhao

IPC: H01L29/76 ,  H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08

CPC classification number: H01L29/7848 ,  H01L29/66795 ,  H01L29/785

Abstract: Fin-type transistor fabrication methods and structures are provided having extended embedded stress elements. The methods include, for example: providing a gate structure extending over a fin extending above a substrate; using isotropic etching and anisotropic etching to form an extended cavity within the fin, where the extended cavity in part undercuts the gate structure, and where the using of the isotropic etching and the anisotropic etching deepens the extended cavity into the fin below the undercut gate structure; and forming an embedded stress element at least partially within the extended cavity, including below the gate structure.

Abstract translation: 鳍型晶体管制造方法和结构被提供具有延伸的嵌入应力元件。 所述方法包括例如：提供在衬底上延伸的翅片上延伸的栅极结构; 使用各向同性蚀刻和各向异性蚀刻在翅片内形成延伸空腔，其中延伸空腔部分地削弱了栅极结构，并且其中使用各向同性蚀刻和各向异性蚀刻将扩展腔加深到底切栅结构下方的翅片 ; 以及至少部分地在所述延伸空腔内形成嵌入的应力元件，包括在所述栅极结构下方。

公开(公告)号：US08846464B1

公开(公告)日：2014-09-30

申请号：US13799814

申请日：2013-03-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bingwu Liu ,  Baofu Zhu ,  Nam Sung Kim

IPC: H01L21/338 ,  H01L29/66

CPC classification number: H01L29/66545 ,  H01L21/28123 ,  H01L29/165 ,  H01L29/49 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/78

Abstract: An approach for controlling a critical dimension (CD) of a RMG of a semiconductor device is provided. Specifically, embodiments of the present invention allow for CD consistency between a dummy gate and a subsequent RMG. In a typical embodiment, a dummy gate having a cap layer is formed over a substrate. A re-oxide layer is then formed over the substrate and around the dummy gate. A set of doping implants will then be implanted in the substrate, and the re-oxide layer will subsequently be removed (after the set of doping implants have been implanted). A set of spacers will then be formed along a set of side walls of the dummy gate and an epitaxial layer will be formed around the set of side walls. Thereafter, the dummy gate will be replaced with a metal gate (e.g., an aluminum or tungsten body having a high-k metal liner there-around).

Abstract translation: 提供了一种用于控制半导体器件的RMG的临界尺寸（CD）的方法。 具体地，本发明的实施例允许伪门和随后的RMG之间的CD一致性。 在典型的实施例中，在衬底上形成具有盖层的虚拟栅极。 然后在衬底上并围绕虚拟栅极形成再氧化物层。 然后将一组掺杂植入物植入衬底中，并且随后将去除再氧化物层（在植入了该组掺杂植入物之后）。 然后将沿着伪栅极的一组侧壁形成一组间隔物，并且将在该组侧壁周围形成外延层。 此后，虚拟栅极将被金属栅极（例如，具有高k金属衬垫的铝或钨体）替代。

公开(公告)号：US09735152B2

公开(公告)日：2017-08-15

申请号：US14315602

申请日：2014-06-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Bingwu Liu

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L29/6656 ,  H01L29/6681

Abstract: A starting non-planar semiconductor structure is provided having a semiconductor substrate, raised semiconductor structures coupled to the substrate, and a layer of isolation material(s) surrounding the raised structures. The isolation layer is recessed to expose about 40 nm to about 70 nm of the raised structures. The increased height of the exposed raised structures, compared to conventional, allows for a taller gate and taller spacers, which reduces undercut under the spacers and short-channel effects from the loss of isolation material in fabrication.

公开(公告)号：US09576856B2

公开(公告)日：2017-02-21

申请号：US14524628

申请日：2014-10-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Bingwu Liu

IPC: H01L21/311 ,  H01L21/8238

CPC classification number: H01L21/823807 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66772 ,  H01L29/775 ,  H01L29/7842 ,  H01L29/7847 ,  H01L29/78696

Abstract: Methods are presented for facilitating fabrication of nanowire structures, such as one or more nanowire field effect transistors. The methods include, for instance: providing a substrate; providing first material layers and second material layers above the substrate, the first material layers interleaved with the second material layers; removing portions of the first material layers and second material layers, the removing forming a plurality of nanowire stacks, including first material nanowires and second material nanowires; removing the first material nanowires from at least one nanowire stack; and removing the second material nanowires from at least one other nanowire stack, where the at least one nanowire stack and at least one other nanowire stack include a p-type nanowire stack(s) and a n-type nanowire stack(s), respectively.

Abstract translation: 提出了用于促进纳米线结构的制造的方法，例如一个或多个纳米线场效应晶体管。 所述方法包括，例如：提供基底; 在所述衬底上方提供第一材料层和第二材料层，所述第一材料层与所述第二材料层交错; 去除第一材料层和第二材料层的部分，去除形成多个纳米线堆叠，包括第一材料纳米线和第二材料纳米线; 从至少一个纳米线堆叠去除所述第一材料纳米线; 以及从至少一个其它纳米线堆叠去除所述第二材料纳米线，其中所述至少一个纳米线堆叠和至少一个其它纳米线堆叠分别包括p型纳米线堆叠和n型纳米线堆叠 。

公开(公告)号：US09337197B1

公开(公告)日：2016-05-10

申请号：US14525763

申请日：2014-10-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Bingwu Liu

IPC: H01L21/20 ,  H01L21/36 ,  H01L21/40 ,  H01L27/092 ,  H01L29/161 ,  H01L29/16 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/7838 ,  H01L21/0217 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/84 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161

Abstract: In one aspect there is set forth herein a semiconductor structure having fins extending upwardly from an ultrathin body (UTB). In one embodiment a multilayer structure can be disposed on a wafer and can be used to pattern voids extending from a UTB layer of the wafer. Selected material can be formed in the voids to define fins extending upward from the UTB layer. In one embodiment silicon (Si) can be grown within the voids to define the fins. In one embodiment, germanium based material can be grown within the voids to define the fins.

Abstract translation: 在一个方面，这里提出了具有从超薄体（UTB）向上延伸的翅片的半导体结构。 在一个实施例中，多层结构可以设置在晶片上，并且可用于图案从晶片的UTB层延伸的空隙。 所选择的材料可以形成在空隙中以限定从UTB层向上延伸的翅片。 在一个实施例中，硅（Si）可以在空隙内生长以限定翅片。 在一个实施例中，锗基材料可以在空隙内生长以限定翅片。

公开(公告)号：US09324713B1

公开(公告)日：2016-04-26

申请号：US14658279

申请日：2015-03-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  Bingwu Liu ,  Hui Zang ,  Lun Zhao

IPC: H01L21/8238 ,  H01L27/088 ,  H01L29/66 ,  H01L29/06 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/3083 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/762 ,  H01L21/76229 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: Method for forming FinFET source/drain regions with reduced field oxide loss and the resulting devices are disclosed. Embodiments include forming silicon fins separated by a field oxide on a silicon substrate; recessing the field oxide to reveal an upper portion of the silicon fins; forming a spacer layer conformally over the upper portion of the fins and over the field oxide; filling spaces between the fins with a material having high selectivity with the spacer layer; recessing the material; removing the spacer layer above an upper surface of the material; removing the material; recessing the upper portion of the fins; and epitaxially growing source/drain regions on the recessed fins.

Abstract translation: 公开了用于形成具有减小的场氧化物损耗的FinFET源极/漏极区域的方法以及所得到的器件。 实施例包括在硅衬底上形成由场氧化物分离的硅散热片; 凹陷场氧化物以露出硅散热片的上部; 在翅片的上部和场氧化物上方形成间隔层; 用具有间隔层的高选择性的材料填充翅片之间的空间; 凹陷材料; 在所述材料的上表面上方移除所述间隔层; 去除材料; 使翅片的上部凹陷; 并且在凹陷散热片上外延生长源极/漏极区域。

公开(公告)号：US09252203B2

公开(公告)日：2016-02-02

申请号：US14271515

申请日：2014-05-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Bingwu Liu

IPC: H01L21/02 ,  H01L49/02 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide improved metal-insulator-metal (MIM) capacitors. In embodiments, series resistance is reduced by forming a via underneath the bottom plate of a MIM capacitor, leading to a metallization layer or intermediate metal sublayer. In embodiments, the MIM capacitor is formed with a corrugated shape to increase the plate surface area, allowing a thicker dielectric to be used, thereby mitigating leakage issues.

Abstract translation: 本发明的实施例提供改进的金属 - 绝缘体 - 金属（MIM）电容器。 在实施例中，通过在MIM电容器的底板下面形成通孔，导致金属化层或中间金属子层来减小串联电阻。 在实施例中，MIM电容器形成为波纹形状以增加板表面积，允许使用更厚的电介质，从而减轻漏电问题。

公开(公告)号：US20150325635A1

公开(公告)日：2015-11-12

申请号：US14271515

申请日：2014-05-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Bingwu Liu

IPC: H01L49/02 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide improved metal-insulator-metal (MIM) capacitors. In embodiments, series resistance is reduced by forming a via underneath the bottom plate of a MIM capacitor, leading to a metallization layer or intermediate metal sublayer. In embodiments, the MIM capacitor is formed with a corrugated shape to increase the plate surface area, allowing a thicker dielectric to be used, thereby mitigating leakage issues.

Abstract translation: 本发明的实施例提供改进的金属 - 绝缘体 - 金属（MIM）电容器。 在实施例中，通过在MIM电容器的底板下面形成通孔，导致金属化层或中间金属子层来减小串联电阻。 在实施例中，MIM电容器形成为波纹形状以增加板表面积，允许使用更厚的电介质，从而减轻漏电问题。