公开(公告)号：US09633915B1

公开(公告)日：2017-04-25

申请号：US15057727

申请日：2016-03-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Dongsuk Park ,  Yue Zhou ,  Mert Karakoy

IPC: H01L21/66 ,  H01J37/28 ,  G01B15/00

CPC classification number: H01J37/28 ,  G03F7/70633 ,  G03F7/70683 ,  H01L22/12

Abstract: Methodologies for using dummy patterns for overlay target design and overlay control are provided. Embodiments include providing a first dummy pattern on a first layer as an outer overlay target for an integrated circuit (IC); providing a pattern associated with a second dummy pattern on a second layer as a target for measuring overlay; and utilizing a scanning electron microscope (SEM) to obtain an overlay measurement between the first and second dummy patterns.

公开(公告)号：US10483214B2

公开(公告)日：2019-11-19

申请号：US15860775

申请日：2018-01-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xintuo Dai ,  Dongsuk Park ,  Guoxiang Ning ,  Mert Karakoy

IPC: H01L23/544 ,  H01L21/66 ,  G03F7/20

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to overlay structures and methods of manufacture. The method includes locating a first plurality of offset dummy features in a first layer; locating a second plurality of offset dummy features in a second layer; measuring a distance between the first plurality of offset dummy features and the second plurality of offset dummy features; and determining that the first layer or the second layer is shifted with respect to one another based on the measurement.