公开(公告)号：US10804170B2

公开(公告)日：2020-10-13

申请号：US16298309

申请日：2019-03-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hongliang Shen ,  Guoxiang Ning ,  Erfeng Ding ,  Dongsuk Park ,  Xiaoxiao Zhang ,  Lan Yang

IPC: H01L21/66 ,  H01L27/02 ,  H01L27/088 ,  G06F30/20 ,  G06F30/398 ,  G06F111/04 ,  G06F111/20

Abstract: The present disclosure relates to a method which includes generating a device layout of an eBeam based overlay (EBO OVL) structure with a minimum design rule, simulating a worst case process margin for the generated device layout of the EBO OVL structure, enabling a plurality of devices for the simulated worst case process margin for the generated device layout of the EBO OVL structure, and breaking a plurality of design rules for the enabled plurality of devices of the EBO OVL structure to generate an OVL measurement layout of the EBO OVL structure.

公开(公告)号：US10705435B2

公开(公告)日：2020-07-07

申请号：US15869150

申请日：2018-01-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Dongyue Yang ,  Xintuo Dai ,  Dongsuk Park ,  Minghao Tang ,  Md Motasim Bellah ,  Pavan Kumar Chinthamanipeta Sripadarao ,  Cheuk Wun Wong

IPC: G03F7/20 ,  G03F9/00

Abstract: Two pairs of alignment targets (one aligned, one misaligned by a bias distance) are formed on different masks to produce a first pair of conjugated interference patterns. Other pairs of alignment targets are also formed on the masks to produce a second pair of conjugated interference patterns that are inverted the first. Misalignment of the dark and light regions of the first interference patterns and the second interference patterns in both pairs of conjugated interference patterns is determined when patterns formed using the masks are overlaid. A magnification factor (of the interference pattern misalignment to the target misalignment) is calculated as a ratio of the difference of misalignment of the relatively dark and relatively light regions in the pairs of interference patterns, over twice the bias distance. The interference pattern misalignment is divided by the magnification factor to produce a self-referenced and self-calibrated target misalignment amount, which is then output.

公开(公告)号：US09633915B1

公开(公告)日：2017-04-25

申请号：US15057727

申请日：2016-03-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Dongsuk Park ,  Yue Zhou ,  Mert Karakoy

IPC: H01L21/66 ,  H01J37/28 ,  G01B15/00

CPC classification number: H01J37/28 ,  G03F7/70633 ,  G03F7/70683 ,  H01L22/12

Abstract: Methodologies for using dummy patterns for overlay target design and overlay control are provided. Embodiments include providing a first dummy pattern on a first layer as an outer overlay target for an integrated circuit (IC); providing a pattern associated with a second dummy pattern on a second layer as a target for measuring overlay; and utilizing a scanning electron microscope (SEM) to obtain an overlay measurement between the first and second dummy patterns.

公开(公告)号：US10733354B2

公开(公告)日：2020-08-04

申请号：US16225199

申请日：2018-12-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hojin Kim ,  Dongyue Yang ,  Dong-Ick Lee ,  Yue Zhou ,  Jae Ho Joung ,  Gregory Costrini ,  El Mehdi Bazizi ,  Dongsuk Park

IPC: G06F30/398

Abstract: Disclosed are embodiments of a system, method and computer program product for wafer-level design including chip and frame design. The embodiments employ three-dimensional (3D) emulation to preliminarily verify in-kerf optical macros included in a frame design layout. Specifically, 3D images of a given in-kerf optical macro at different process steps are generated by a 3D emulator and a determination is made as to whether or not that macro will be formed as predicted. If not, the plan for the macro is altered using an iterative design process. Once the in-kerf optical macros within the frame design layout have been preliminarily verified, wafer-level design layout verification, including chip and frame design layout verification, is performed. Once the wafer-level design layout has been verified, wafer-level design layout validation, including chip and frame design layout validation, is performed. Optionally, an emulation library can store results of 3D emulation processes for future use.

公开(公告)号：US20190219930A1

公开(公告)日：2019-07-18

申请号：US15869150

申请日：2018-01-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Dongyue Yang ,  Xintuo Dai ,  Dongsuk Park ,  Minghao Tang ,  Md Motasim Bellah ,  Pavan Kumar Chinthamanipeta Sripadarao ,  Cheuk Wun Wong

IPC: G03F7/20 ,  G03F9/00

Abstract: Two pairs of alignment targets (one aligned, one misaligned by a bias distance) are formed on different masks to produce a first pair of conjugated interference patterns. Other pairs of alignment targets are also formed on the masks to produce a second pair of conjugated interference patterns that are inverted the first. Misalignment of the dark and light regions of the first interference patterns and the second interference patterns in both pairs of conjugated interference patterns is determined when patterns formed using the masks are overlaid. A magnification factor (of the interference pattern misalignment to the target misalignment) is calculated as a ratio of the difference of misalignment of the relatively dark and relatively light regions in the pairs of interference patterns, over twice the bias distance. The interference pattern misalignment is divided by the magnification factor to produce a self-referenced and self-calibrated target misalignment amount, which is then output.

公开(公告)号：US10103070B2

公开(公告)日：2018-10-16

申请号：US14671265

申请日：2015-03-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Dongsuk Park ,  Wangkeun Cho ,  Wen Hua Cheng

IPC: H01L21/66 ,  G01B21/08 ,  G01B21/04

Abstract: Methods and processes for forming semiconductor devices with reduced yield loss and failed dies are provided. One method includes, for instance: obtaining a wafer after at least one fabrication processing; taking first r, θ, z measurements of the wafer after the at least one fabrication processing; performing at least one second fabrication processing; taking second r, θ, z measurements of the wafer after the at least one second fabrication processing; and analyzing the second r, θ, z measurements with respect to the first r, θ, z measurements. A process includes, for instance: obtaining a wafer with a substrate and at least one first device positioned on the substrate; taking first measurements in a r, θ, z coordinate system; forming at least one second device over the substrate; taking second measurements in the r, θ, z coordinate system; and analyzing the second measurements with respect to the first measurements.

公开(公告)号：US20200241429A1

公开(公告)日：2020-07-30

申请号：US16847721

申请日：2020-04-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Dongyue Yang ,  Xintuo Dai ,  Dongsuk Park ,  Minghao Tang ,  Md Motasim Bellah ,  Pavan Kumar Chinthamanipeta Sripadarao ,  Cheuk Wun Wong

IPC: G03F7/20 ,  G03F9/00

Abstract: Two pairs of alignment targets (one aligned, one misaligned by a bias distance) are formed on different masks to produce a first pair of conjugated interference patterns. Other pairs of alignment targets are also formed on the masks to produce a second pair of conjugated interference patterns that are inverted the first. Misalignment of the dark and light regions of the first interference patterns and the second interference patterns in both pairs of conjugated interference patterns is determined when patterns formed using the masks are overlaid. A magnification factor (of the interference pattern misalignment to the target misalignment) is calculated as a ratio of the difference of misalignment of the relatively dark and relatively light regions in the pairs of interference patterns, over twice the bias distance. The interference pattern misalignment is divided by the magnification factor to produce a self-referenced and self-calibrated target misalignment amount, which is then output.

公开(公告)号：US10483214B2

公开(公告)日：2019-11-19

申请号：US15860775

申请日：2018-01-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xintuo Dai ,  Dongsuk Park ,  Guoxiang Ning ,  Mert Karakoy

IPC: H01L23/544 ,  H01L21/66 ,  G03F7/20

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to overlay structures and methods of manufacture. The method includes locating a first plurality of offset dummy features in a first layer; locating a second plurality of offset dummy features in a second layer; measuring a distance between the first plurality of offset dummy features and the second plurality of offset dummy features; and determining that the first layer or the second layer is shifted with respect to one another based on the measurement.