公开(公告)号：US20150037945A1

公开(公告)日：2015-02-05

申请号：US13956475

申请日：2013-08-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Johannes M. van Meer ,  Michael J. Hargrove ,  Christian Gruensfelder ,  Yanxiang Liu ,  Srikanth B. Samavedam

IPC: H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/7856 ,  H01L21/02636 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/1608 ,  H01L29/66795 ,  H01L29/7855

Abstract: Approaches for enabling epitaxial growth of silicon fins in a device (e.g., a fin field effect transistor device (FinFET)) are provided. Specifically, approaches are provided for forming a set of silicon fins for a FinFET device, the FinFET device comprising: a set of gate structures formed over a substrate, each of the set of gate structures including a capping layer and a set of spacers; an oxide fill formed over the set of gate structures; a set of openings formed in the device by removing the capping layer and the set of spacers from one or more of the set of gate structures; a silicon material epitaxially grown within the set of openings in the device and then planarized; and wherein the oxide fill is etched to expose the silicon material and form the set of fins.

公开(公告)号：US09437740B2

公开(公告)日：2016-09-06

申请号：US14686228

申请日：2015-04-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Johannes M. van Meer ,  Michael J. Hargrove ,  Christian Gruensfelder ,  Yanxiang Liu ,  Srikanth B. Samavedam

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/16 ,  H01L21/02

CPC classification number: H01L29/7856 ,  H01L21/02636 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/1608 ,  H01L29/66795 ,  H01L29/7855

Abstract: Approaches for enabling epitaxial growth of silicon fins in a device (e.g., a fin field effect transistor device (FinFET)) are provided. Specifically, approaches are provided for forming a set of silicon fins for a FinFET device, the FinFET device comprising: a set of gate structures formed over a substrate, each of the set of gate structures including a capping layer and a set of spacers; an oxide fill formed over the set of gate structures; a set of openings formed in the device by removing the capping layer and the set of spacers from one or more of the set of gate structures; a silicon material epitaxially grown within the set of openings in the device and then planarized; and wherein the oxide fill is etched to expose the silicon material and form the set of fins.

公开(公告)号：US09530864B2

公开(公告)日：2016-12-27

申请号：US14314404

申请日：2014-06-25

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Steven J. Bentley ,  Michael J. Hargrove ,  Chia-Yu Chen ,  Ryan O. Jung ,  Sivanandha K. Kanakasabapathy ,  Tenko Yamashita

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7836

Abstract: Approaches for providing junction overlap control in a semiconductor device are provided. Specifically, at least one approach includes: providing a gate over a substrate; forming a set of junction extensions in a channel region adjacent the gate; forming a set of spacer layers along each of a set of sidewalls of the gate; removing the gate between the set of spacer layers to form an opening; removing, from within the opening, an exposed sacrificial spacer layer of the set of spacer layers, the exposed sacrificial spacer layer defining a junction extension overlap linear distance from the set of sidewalls of the gate; and forming a replacement gate electrode within the opening. This results in a highly scaled advanced transistor having precisely defined junction profiles and well-controlled gate overlap geometry achieved using extremely abrupt junctions whose surface position is defined using the set of spacer layers.

Abstract translation: 提供了在半导体器件中提供接合重叠控制的方法。 具体地，至少一种方法包括：在衬底上提供栅极; 在与栅极相邻的沟道区域中形成一组结延伸部分; 沿着栅极的一组侧壁中的每一个形成一组间隔层; 移除所述一组间隔层之间的栅极以形成开口; 从所述开口内去除所述一组间隔层的暴露的牺牲间隔层，所述暴露的牺牲间隔层限定结延伸部与所述栅极侧壁的所述一组侧壁重叠线性距离; 以及在所述开口内形成替换栅电极。 这导致具有精确限定的接合轮廓的高度缩放的先进晶体管，并且使用极其突出的接头实现良好控制的栅极重叠几何，其表面位置使用该组间隔层限定。

公开(公告)号：US20150380514A1

公开(公告)日：2015-12-31

申请号：US14314404

申请日：2014-06-25

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Steven J. Bentley ,  Michael J. Hargrove ,  Chia-Yu Chen ,  Ryan O. Jung ,  Sivanandha K. Kanakasabapathy ,  Tenko Yamashita

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7836

Abstract: Approaches for providing junction overlap control in a semiconductor device are provided. Specifically, at least one approach includes: providing a gate over a substrate; forming a set of junction extensions in a channel region adjacent the gate; forming a set of spacer layers along each of a set of sidewalls of the gate; removing the gate between the set of spacer layers to form an opening; removing, from within the opening, an exposed sacrificial spacer layer of the set of spacer layers, the exposed sacrificial spacer layer defining a junction extension overlap linear distance from the set of sidewalls of the gate; and forming a replacement gate electrode within the opening. This results in a highly scaled advanced transistor having precisely defined junction profiles and well-controlled gate overlap geometry achieved using extremely abrupt junctions whose surface position is defined using the set of spacer layers.

Abstract translation: 提供了在半导体器件中提供接合重叠控制的方法。 具体地，至少一种方法包括：在衬底上提供栅极; 在与栅极相邻的沟道区域中形成一组结延伸部分; 沿着栅极的一组侧壁中的每一个形成一组间隔层; 移除所述一组间隔层之间的栅极以形成开口; 从所述开口内去除所述一组间隔层的暴露的牺牲间隔层，所述暴露的牺牲间隔层限定结延伸部与所述栅极侧壁的所述一组侧壁重叠线性距离; 以及在所述开口内形成替换栅电极。 这导致具有精确限定的接合轮廓的高度缩放的先进晶体管，并且使用极其突出的接头实现良好控制的栅极重叠几何，其表面位置使用该组间隔层限定。

公开(公告)号：US20150221770A1

公开(公告)日：2015-08-06

申请号：US14686228

申请日：2015-04-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Johannes M. van Meer ,  Michael J. Hargrove ,  Christian Gruensfelder ,  Yanxiang Liu ,  Srikanth B. Samavedam

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/7856 ,  H01L21/02636 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/1608 ,  H01L29/66795 ,  H01L29/7855

Abstract: Approaches for enabling epitaxial growth of silicon fins in a device (e.g., a fin field effect transistor device (FinFET)) are provided. Specifically, approaches are provided for forming a set of silicon fins for a FinFET device, the FinFET device comprising: a set of gate structures formed over a substrate, each of the set of gate structures including a capping layer and a set of spacers; an oxide fill formed over the set of gate structures; a set of openings formed in the device by removing the capping layer and the set of spacers from one or more of the set of gate structures; a silicon material epitaxially grown within the set of openings in the device and then planarized; and wherein the oxide fill is etched to expose the silicon material and form the set of fins.

Abstract translation: 提供了用于在器件（例如，鳍式场效应晶体管器件（FinFET））中实现硅鳍外延生长的方法。 具体地，提供了用于形成用于FinFET器件的一组硅散热片的方法，所述FinFET器件包括：在衬底上形成的一组栅极结构，所述一组栅极结构中的每一个包括覆盖层和一组间隔物; 在该组栅极结构上形成的氧化物填充物; 通过从所述一组或多组所述栅极结构中去除所述覆盖层和所述一组间隔物而在所述器件中形成的一组开口; 外延生长在器件中的开口组内然后平坦化的硅材料; 并且其中蚀刻氧化物填充物以暴露硅材料并形成该组散热片。

公开(公告)号：US09034737B2

公开(公告)日：2015-05-19

申请号：US13956475

申请日：2013-08-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Johannes M. van Meer ,  Michael J. Hargrove ,  Christian Gruensfelder ,  Yanxiang Liu ,  Srikanth B. Samavedam

IPC: H01L21/20 ,  H01L21/36 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/7856 ,  H01L21/02636 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/1608 ,  H01L29/66795 ,  H01L29/7855

Abstract: Approaches for enabling epitaxial growth of silicon fins in a device (e.g., a fin field effect transistor device (FinFET)) are provided. Specifically, approaches are provided for forming a set of silicon fins for a FinFET device, the FinFET device comprising: a set of gate structures formed over a substrate, each of the set of gate structures including a capping layer and a set of spacers; an oxide fill formed over the set of gate structures; a set of openings formed in the device by removing the capping layer and the set of spacers from one or more of the set of gate structures; a silicon material epitaxially grown within the set of openings in the device and then planarized; and wherein the oxide fill is etched to expose the silicon material and form the set of fins.

Abstract translation: 提供了用于在器件（例如，鳍式场效应晶体管器件（FinFET））中实现硅鳍外延生长的方法。 具体地，提供了用于形成用于FinFET器件的一组硅散热片的方法，所述FinFET器件包括：在衬底上形成的一组栅极结构，所述一组栅极结构中的每一个包括覆盖层和一组间隔物; 在该组栅极结构上形成的氧化物填充物; 通过从所述一组或多组所述栅极结构中去除所述覆盖层和所述一组间隔物而在所述器件中形成的一组开口; 外延生长在器件中的开口组内然后平坦化的硅材料; 并且其中蚀刻氧化物填充物以暴露硅材料并形成该组散热片。