公开(公告)号：US20180069092A1

公开(公告)日：2018-03-08

申请号：US15258333

申请日：2016-09-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Srikanth Balaji SAMAVEDAN ,  Manfred ELLER ,  Min-hwa CHI ,  Hui ZANG

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L29/66545 ,  H01L21/30604 ,  H01L21/3085 ,  H01L29/0649 ,  H01L29/4236 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of reducing parasitic capacitance includes providing a starting semiconductor structure, the starting semiconductor structure including a semiconductor substrate with fin(s) thereon, the fin(s) having at least two dummy transistors integrated therewith and separated by a dielectric region, the dummy transistors including dummy gates with spacers and gate caps, the fin(s) having ends tucked by the dummy gates. The method further includes removing the dummy gates and gate caps, resulting in gate trenches, protecting area(s) of the structure during fabrication process(es) where source/drain parasitic capacitance may occur, and forming air-gaps at a bottom portion of unprotected gate trenches to reduce parasitic capacitance. The resulting semiconductor structure includes a semiconductor substrate with fin(s) thereon, FinFET(s) integral with the fin(s), the FinFET(s) including a gate electrode, a gate liner lining the gate electrode, and air-gap(s) in gate trench(es) of the FinFET(s), reducing parasitic capacitance by at least about 75 percent as compared to no air-gaps.

公开(公告)号：US20180277655A1

公开(公告)日：2018-09-27

申请号：US15994614

申请日：2018-05-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Srikanth Balaji SAMAVEDAN ,  Manfred ELLER ,  Min-hwa CHI ,  Hui ZANG

IPC: H01L29/66 ,  H01L21/308 ,  H01L21/306 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/66545 ,  H01L21/30604 ,  H01L21/3085 ,  H01L29/0649 ,  H01L29/4236 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of reducing parasitic capacitance includes providing a starting semiconductor structure, the starting semiconductor structure including a semiconductor substrate with fin(s) thereon, the fin(s) having at least two dummy transistors integrated therewith and separated by a dielectric region, the dummy transistors including dummy gates with spacers and gate caps, the fin(s) having ends tucked by the dummy gates. The method further includes removing the dummy gates and gate caps, resulting in gate trenches, protecting area(s) of the structure during fabrication process(es) where source/drain parasitic capacitance may occur, and forming air-gaps at a bottom portion of unprotected gate trenches to reduce parasitic capacitance. The resulting semiconductor structure includes a semiconductor substrate with fin(s) thereon, FinFET(s) integral with the fin(s), the FinFET(s) including a gate electrode, a gate liner lining the gate electrode, and air-gap(s) in gate trench(es) of the FinFET(s), reducing parasitic capacitance by at least about 75 percent as compared to no air-gaps.