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    SINGLE DIFFUSION CUT FOR GATE STRUCTURES
    1.
    发明申请
    SINGLE DIFFUSION CUT FOR GATE STRUCTURES 有权

    公开(公告)号：US20200176444A1

    公开(公告)日：2020-06-04

    申请号：US16204506

    申请日：2018-11-29

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Guowei XU ,  Hui ZANG ,  Ruilong XIE ,  Haiting WANG

    IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66

    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a single diffusion cut for gate structures and methods of manufacture. The structure includes: a plurality of fin structures composed of semiconductor material; a plurality of replacement gate structures extending over the plurality of fin structures; a plurality of diffusion regions adjacent to the each of the plurality of replacement gate structures; and a single diffusion break between the diffusion regions of the adjacent replacement gate structures, the single diffusion break being filled with an insulator material. In a first cross-sectional view, the single diffusion break extends into the semiconductor material and in a second cross-sectional view, the single diffusion break is devoid of semiconductor material of the plurality of fin structures.

    FINFET WITH ETCH-SELECTIVE SPACER AND SELF-ALIGNED CONTACT CAPPING LAYER
    2.
    发明申请
    FINFET WITH ETCH-SELECTIVE SPACER AND SELF-ALIGNED CONTACT CAPPING LAYER 审中-公开

    公开(公告)号：US20190164898A1

    公开(公告)日：2019-05-30

    申请号：US15823899

    申请日：2017-11-28

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Hui ZANG ,  Guowei XU ,  Scott BEASOR ,  Ruilong Xie

    IPC: H01L23/532 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L21/311

    Abstract: In the manufacture of a FinFET device, an isolation architecture is provided between gate and source/drain contact locations. The isolation architecture may include a low-k spacer layer and a contact etch stop layer. An upper portion of the isolation architecture is removed and replaced with a high-k, etch-selective spacer layer adapted to resist degradation during an etch to open the source/drain contact locations. The high-k spacer layer, in conjunction with a self-aligned contact (SAC) capping layer disposed over the gate and overlapping a sidewall of the isolation layer, forms an improved isolation structure that inhibits short circuits or parasitic capacitance between the gate and source/drain contacts.

    VERTICAL SRAM STRUCTURE WITH PENETRATING CROSS-COUPLED CONTACTS
    5.
    发明申请
    VERTICAL SRAM STRUCTURE WITH PENETRATING CROSS-COUPLED CONTACTS 审中-公开

    公开(公告)号：US20190027483A1

    公开(公告)日：2019-01-24

    申请号：US16056660

    申请日：2018-08-07

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Hui ZANG ,  Manfred ELLER ,  Kwan-Yong LIM

    IPC: H01L27/11 ,  H01L29/66 ,  H01L29/78

    Abstract: A vertical SRAM cell includes a first (1st) inverter having a 1st common gate structure operatively connecting channels of a 1st pull-up (PU) and a 1st pull-down (PD) transistor. A 1st metal contact electrically connects bottom source/drain (S/D) regions of the 1st PU and 1st PD transistors. A second (2nd) inverter has a 2nd common gate structure operatively connecting channels of a 2nd PU and a 2nd PD transistor. A 2nd metal contact electrically connects bottom S/D regions of the 2nd PU and 2nd PD transistors. A 1st cross-coupled contact electrically connects the 2nd common gate structure to the 1st metal contact. The 2nd common gate structure entirely surrounds a perimeter of the 1st cross-coupled contact. A 2nd cross-coupled contact electrically connects the 1st common gate structure to the 2nd metal contact. The 1st common gate structure entirely surrounds a perimeter of the 2nd cross-coupled contact.

    SOI-BASED SEMICONDUCTOR DEVICE WITH DYNAMIC THRESHOLD VOLTAGE
    8.
    发明申请
    SOI-BASED SEMICONDUCTOR DEVICE WITH DYNAMIC THRESHOLD VOLTAGE 有权
    具有动态阈值电压的基于SOI的半导体器件

    公开(公告)号：US20170018573A1

    公开(公告)日：2017-01-19

    申请号：US14801519

    申请日：2015-07-16

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Hui ZANG ,  Manfred ELLER

    IPC: H01L27/12 ,  H01L29/66 ,  H01L21/84

    CPC classification number: H01L27/1203 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L29/66553 ,  H01L29/66772 ,  H01L29/78648

    Abstract: A semiconductor device includes a semiconductor substrate, an insulating layer on a top surface of the substrate, and a first semiconductor transistor on the insulating layer, the transistor including an active region with a source region, a drain region, a channel region between the source and drain regions and a gate structure over the channel region, the gate structure extending beyond the transistor to an adjacent area. An outer well is included in the substrate, an inner well of an opposite type as the outer well situated within the outer well and under the active region and adjacent area, and a contact for the inner well in the adjacent area, the contact surrounding the gate structure. Operating the device includes applying a variable voltage at the contact for the inner well, a threshold voltage for the first transistor being altered by the variable voltage. The inner well and gate may be exposed and contacts created therefor together.

    Abstract translation: 半导体器件包括半导体衬底，衬底顶表面上的绝缘层和绝缘层上的第一半导体晶体管，晶体管包括有源区，源区，漏区，源极之间的沟道区 漏极区和沟道区上的栅极结构，栅极结构延伸超过晶体管到相邻区域。 外部孔包括在衬底中，与外部阱中位于外部阱内并且在有源区域和相邻区域下方的相反类型的内部阱以及相邻区域中的内部阱的接触，围绕 门结构。 操作器件包括在内部阱的触点处施加可变电压，第一晶体管的阈值电压被可变电压改变。 内部井和闸门可能被暴露，并且一起形成了与之相联系的接触。

    FABRICATING STACKED NANOWIRE, FIELD-EFFECT TRANSISTORS
    10.
    发明申请
    FABRICATING STACKED NANOWIRE, FIELD-EFFECT TRANSISTORS 有权
    制造堆叠的纳米级，场效应晶体管

    公开(公告)号：US20160155800A1

    公开(公告)日：2016-06-02

    申请号：US14988050

    申请日：2016-01-05

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Hui ZANG ,  Guillaume BOUCHE ,  Gabriel Padron WELLS

    IPC: H01L29/06 ,  H01L29/78 ,  H01L29/161 ,  H01L21/308 ,  H01L29/16

    CPC classification number: H01L29/0673 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/16 ,  H01L29/161 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

    Abstract: Methods are presented for facilitating fabricating stacked nanowire, field-effect transistors. The methods include: forming a cut mask spacer on a gate structure disposed above multiple layers above a substrate structure, the gate structure including a sidewall spacer along its sidewalls, and the cut mask spacer overlying the sidewall spacer; defining a stack structure by cutting through the multiple layers using the cut mask spacer and gate structure as a mask, and selectively etching at least one layer of the multiple layers to undercut, in part, the mask, where at least one other layer of the multiple layers remains un-etched by the selectively etching; and providing an alignment mask spacer over the gate structure and over end surfaces of the multiple layers below the gate structure, the alignment mask spacer facilitating etching the other layer(s) of the multiple layers to selectively expose, in part, end surfaces of the other layer(s).

    Abstract translation: 提出了用于促进制造堆叠的纳米线，场效应晶体管的方法。 所述方法包括：在栅极结构上形成切割掩模间隔物，栅极结构设置在衬底结构上方的多层上方，栅极结构包括沿其侧壁的侧壁间隔物和覆盖侧壁间隔物的切割掩模间隔物; 通过使用切割掩模间隔物和栅极结构作为掩模切割多个层来限定堆叠结构，并且部分地选择性地蚀刻多个层的至少一个层以部分地掩盖掩模，其中至少一个其它层 通过选择性蚀刻，多层保持未蚀刻; 并且在栅极结构的栅极结构和多个层的上端表面上提供对准掩模间隔物，所述对准掩模间隔物有助于蚀刻多个层的另一层，以选择性地暴露部分端部表面 其他层。

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