公开(公告)号：US20170338247A1

公开(公告)日：2017-11-23

申请号：US15160623

申请日：2016-05-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Manfred ELLER ,  Min-hwa CHI

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L27/11

CPC classification number: H01L27/1207 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/1211 ,  H01L29/4966

Abstract: Circuit structures, such as inverters and static random access memories, and fabrication methods thereof are presented. The circuit structures include, for instance: a first transistor, the first transistor having a first channel region disposed above an isolation region; and a second transistor, the second transistor having a second channel region, the second channel region being laterally adjacent to the first channel region of the first transistor and vertically spaced apart therefrom by the isolation region thereof. In one embodiment, the first channel region and the isolation region of the first transistor are disposed above a substrate, and the substrate includes the second channel region of the second transistor.

公开(公告)号：US20170338156A1

公开(公告)日：2017-11-23

申请号：US15156767

申请日：2016-05-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Min-hwa CHI ,  Jinping LIU

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L21/823456 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/4916 ,  H01L29/6653 ,  H01L29/66545

Abstract: A method of adjusting work-function metal thickness includes providing a structure having a substrate, the substrate including a longitudinally extending array of fins disposed thereon. Spacers are then formed on sidewalls of fins of the array. Pillars are formed between and adjacent the spacers. A gate having dummy gate material is formed over the structure, the gate extending laterally across the spacers and fins of the array. The dummy gate material and spacers are removed from the gate to form work-function (WF) metal trenches defined by the pillars and fins within the gate. The WF metal trenches have a first trench width. A thickness of the pillars is adjusted to provide a second trench width, different from the first trench width, for the WF metal trenches. A WF metal structure is disposed within the WF metal trenches.

公开(公告)号：US20170309563A1

公开(公告)日：2017-10-26

申请号：US15137362

申请日：2016-04-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Min-hwa CHI

IPC: H01L23/522 ,  H01L23/528 ,  H01L49/02

CPC classification number: H01L23/5223 ,  H01L23/5226 ,  H01L23/528 ,  H01L28/60

Abstract: A method of forming a semiconductor structure, comprising forming a dual damascene structure having a capacitor trench and an interconnect trench, forming a first electrode a dielectric of the capacitor, and, depositing a metal within said capacitor trench and said interconnection trench wherein the metal forms a second electrode of the capacitor and also forms an interconnection between layers of an interconnecting structure of a semiconductor device. A semiconductor structure, comprising a dual damascene structure having a capacitor trench for a capacitor, the capacitor including a first electrode, a second electrode, and a high-K dielectric between the first and second electrodes, the high-k dielectric configured to seal the first electrode from the second electrode and from subsequent wiring layers of the interconnecting structure of the semiconductor device, and, an interconnection trench for a metal interconnection to form an interconnection between the interconnecting structure of the semiconductor device.

公开(公告)号：US20170141031A1

公开(公告)日：2017-05-18

申请号：US15421698

申请日：2017-02-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chun Yu WONG ,  Jagar SINGH ,  Ashish BARASKAR ,  Min-hwa CHI

IPC: H01L23/525 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L23/5256 ,  H01L21/0226 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/283 ,  H01L21/3205 ,  H01L27/11206 ,  H01L29/0673 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor fuses with nanowire fuse links and fabrication methods thereof are presented. The methods include, for instance: fabricating a semiconductor fuse, the semiconductor fuse including at least one nanowire fuse link, and the fabricating including: forming at least one nanowire, the at least one nanowire including a semiconductor material; and reacting the at least one nanowire with a metal to form the at least one nanowire fuse link of the semiconductor fuse, the at least one nanowire fuse link including a semiconductor-metal alloy. In another aspect, a structure is presented. The structure includes: a semiconductor fuse, the semiconductor fuse including: at least one nanowire fuse link, the at least one nanowire fuse link including a semiconductor-metal alloy.

公开(公告)号：US20170092373A1

公开(公告)日：2017-03-30

申请号：US14867331

申请日：2015-09-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suraj K. PATIL ,  Min-hwa CHI ,  Ajey P. JACOB

IPC: G11C17/16 ,  H01L29/06 ,  H01L23/525 ,  H01L29/78

CPC classification number: G11C17/16 ,  H01L23/5256 ,  H01L29/0673 ,  H01L29/785

Abstract: Programmable devices and fabrication methods thereof are presented. The programmable devices include, for instance, a first electrode and a second electrode electrically connected by a link portion. The link portion includes one material of a metal material or a semiconductor material and the first and second electrodes includes the other material of the metal material or the semiconductor material. For example, the link portion facilitates programming the programmable device by applying a programming current between the first electrode and the second electrode to facilitate migration of the one material of the link portion towards at least one of the first or second electrodes. In one embodiment, the programming current is configured to heat the link portion to facilitate the migration of the one material of the link portion towards the at least one of the first or second electrodes.

公开(公告)号：US20170040110A1

公开(公告)日：2017-02-09

申请号：US14818342

申请日：2015-08-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Min-hwa CHI

IPC: H01G4/012 ,  H01G4/30

CPC classification number: H01G4/012 ,  H01G4/306 ,  H01G4/33 ,  H01L23/5222 ,  H01L28/82 ,  H01L28/90

Abstract: Capacitor structures having first electrodes at least partially embedded within a second electrode, and fabrication methods are presented. The methods include, for instance: providing the first electrodes at least partially within an insulator layer, the first electrodes comprising exposed portions; covering exposed portions of the first electrodes with a dielectric material; and forming the second electrode at least partially around the dielectric covered portions of the first electrodes, the second electrode being physically separated from the first electrodes by the dielectric material. In one embodiment, a method further includes exposing further portions of the first electrodes; and providing a contact structure in electrical contact with the further exposed portions of the first electrodes. In another embodiment, some of the first electrodes are aligned substantially parallel to a first direction and other of the first electrodes are aligned substantially parallel to a second direction, the first and second directions being different directions.

Abstract translation: 具有至少部分地嵌入在第二电极内的第一电极的电容器结构以及制造方法。 所述方法包括例如：至少部分地在绝缘体层内提供第一电极，第一电极包括暴露部分; 用介电材料覆盖第一电极的暴露部分; 以及至少部分地围绕所述第一电极的所述电介质覆盖部分形成所述第二电极，所述第二电极通过所述电介质材料与所述第一电极物理分离。 在一个实施例中，一种方法还包括暴露第一电极的另外部分; 以及提供与第一电极的另外的暴露部分电接触的接触结构。 在另一个实施例中，一些第一电极基本上平行于第一方向排列，而另一些第一电极基本上平行于第二方向排列，第一和第二方向是不同的方向。

公开(公告)号：US20160359056A1

公开(公告)日：2016-12-08

申请号：US14730294

申请日：2015-06-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min-hwa CHI

IPC: H01L29/866 ,  H01L29/66

CPC classification number: H01L29/866 ,  H01L21/306 ,  H01L29/0684 ,  H01L29/0688 ,  H01L29/165 ,  H01L29/66106

Abstract: Diodes and fabrication methods thereof are presented. The diodes include, for instance: a first semiconductor region disposed at least partially within a substrate, the first semiconductor region having a first conductivity type; and a second semiconductor region disposed at least partially within the first semiconductor region, the second semiconductor region having a second conductivity type, wherein the first semiconductor region separates the second semiconductor region from the substrate. In one embodiment, the substrate and the first semiconductor region have a sigma-shaped boundary. In another embodiment, the substrate and the first semiconductor region have U-shaped boundary. In a further embodiment, the first semiconductor region comprises an alloy of a first material and a second material, where the concentration of the second material varies from a maximum to a minimum, where the first semiconductor region adjacent to the second semiconductor region has the minimum of the concentration of the second material.

Abstract translation: 提出了二极管及其制造方法。 二极管包括例如：至少部分地设置在衬底内的第一半导体区域，第一半导体区域具有第一导电类型; 以及至少部分地设置在所述第一半导体区域内的第二半导体区域，所述第二半导体区域具有第二导电类型，其中所述第一半导体区域将所述第二半导体区域与所述衬底分离。 在一个实施例中，衬底和第一半导体区域具有σ形边界。 在另一个实施例中，衬底和第一半导体区域具有U形边界。 在另一实施例中，第一半导体区域包括第一材料和第二材料的合金，其中第二材料的浓度从最大值到最小变化，其中与第二半导体区域相邻的第一半导体区域具有最小值 的第二种材料的浓度。

公开(公告)号：US20160284643A1

公开(公告)日：2016-09-29

申请号：US14865589

申请日：2015-09-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chun Yu WONG ,  Jagar SINGH ,  Ashish BARASKAR ,  Min-hwa CHI

IPC: H01L23/525 ,  H01L29/78 ,  H01L29/06 ,  H01L27/112 ,  H01L23/528 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/283 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L23/5256 ,  H01L21/0226 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/283 ,  H01L21/3205 ,  H01L27/11206 ,  H01L29/0673 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor fuses with nanowire fuse links and fabrication methods thereof are presented. The methods include, for instance: fabricating a semiconductor fuse, the semiconductor fuse including at least one nanowire fuse link, and the fabricating including: forming at least one nanowire, the at least one nanowire including a semiconductor material; and reacting the at least one nanowire with a metal to form the at least one nanowire fuse link of the semiconductor fuse, the at least one nanowire fuse link including a semiconductor-metal alloy. In another aspect, a structure is presented. The structure includes: a semiconductor fuse, the semiconductor fuse including: at least one nanowire fuse link, the at least one nanowire fuse link including a semiconductor-metal alloy.

Abstract translation: 提出了具有纳米线熔断体的半导体熔丝及其制造方法。 所述方法包括例如：制造半导体熔丝，所述半导体熔丝包括至少一个纳米线熔断体，所述制造包括：形成至少一个纳米线，所述至少一个纳米线包括半导体材料; 并且使所述至少一个纳米线与金属反应以形成所述半导体熔丝的所述至少一个纳米线熔断体，所述至少一个纳米线熔断体包括半导体 - 金属合金。 在另一方面，提出了一种结构。 所述结构包括：半导体熔丝，所述半导体熔丝包括：至少一个纳米线熔断体，所述至少一个纳米线熔断体包括半导体 - 金属合金。

公开(公告)号：US20150357332A1

公开(公告)日：2015-12-10

申请号：US14832512

申请日：2015-08-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jin Ping LIU ,  Min-hwa CHI

IPC: H01L27/092 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L27/0886 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: Devices and methods for forming semiconductor devices with FinFETs are provided. One intermediate semiconductor device includes, for instance: a substrate with at least one fin with at least one channel; at least one gate over the channel; at least one hard-mask over the gate; and at least one spacer disposed over the gate and hard-mask. One method includes, for instance: obtaining an intermediate semiconductor device; forming at least one recess into the substrate, the recess including a bottom and at least one sidewall exposing a portion of the at least one fin; depositing a dielectric layer into the at least one recess; removing at least a portion of the dielectric layer to form a barrier dielectric layer; and performing selective epitaxial growth in the at least one recess over the barrier dielectric layer.

公开(公告)号：US20150035018A1

公开(公告)日：2015-02-05

申请号：US13955861

申请日：2013-07-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jin Ping LIU ,  Min-hwa CHI

IPC: H01L29/78 ,  H01L21/306

CPC classification number: H01L27/0924 ,  H01L27/0886 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: Devices and methods for forming semiconductor devices with FinFETs are provided. One intermediate semiconductor device includes, for instance: a substrate with at least one fin with at least one channel; at least one gate over the channel; at least one hard-mask over the gate; and at least one spacer disposed over the gate and hard-mask. One method includes, for instance: obtaining an intermediate semiconductor device; forming at least one recess into the substrate, the recess including a bottom and at least one sidewall exposing a portion of the at least one fin; depositing a dielectric layer into the at least one recess; removing at least a portion of the dielectric layer to form a barrier dielectric layer; and performing selective epitaxial growth in the at least one recess over the barrier dielectric layer.

Abstract translation: 提供了用FinFET形成半导体器件的器件和方法。 一个中间半导体器件包括例如：具有至少一个具有至少一个通道的鳍片的衬底; 通道上至少有一个门; 在门上至少有一个硬掩模; 以及设置在栅极和硬掩模上的至少一个间隔物。 一种方法包括，例如：获得中间半导体器件; 将至少一个凹部形成到所述基底中，所述凹部包括底部和暴露所述至少一个翅片的一部分的至少一个侧壁; 将介电层沉积到所述至少一个凹部中; 去除所述电介质层的至少一部分以形成阻挡介电层; 以及在所述阻挡介电层上的所述至少一个凹槽中进行选择性外延生长。