公开(公告)号：US09905707B1

公开(公告)日：2018-02-27

申请号：US15337026

申请日：2016-10-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andrei Sidelnicov ,  Alban Zaka ,  El Mehdi Bazizi ,  Venkata Naga Ranjith Kumar Nelluri ,  Juergen Faul

IPC: H01L29/00 ,  H01L29/94 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L29/94 ,  H01L21/265 ,  H01L29/66174

Abstract: Capacitive structures in the device level of sophisticated MOS devices may be formed so as to exhibit a significantly reduced capacitance/voltage variability. To this end, a highly doped semiconductor region may be formed in the “channel” of the capacitive structure. For example, for a specified concentration of the dopant species and a specified range of the vertical dimension of the highly doped semiconductor region, a reduced variability of approximately 3% or less may be obtained for a voltage range of, for example, ±5 V.