公开(公告)号：US09899319B2

公开(公告)日：2018-02-20

申请号：US15428604

申请日：2017-02-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andreas Kurz ,  Andrei Sidelnicov

IPC: H01L23/525 ,  H01L29/08 ,  H01L29/06 ,  H01L27/12 ,  H01L29/78

CPC classification number: H01L23/5256 ,  H01L21/02532 ,  H01L21/76264 ,  H01L21/84 ,  H01L23/53209 ,  H01L27/1203 ,  H01L28/00 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/41783 ,  H01L29/66515 ,  H01L29/66628 ,  H01L29/78 ,  H01L29/7838

Abstract: A semiconductor device with a semiconductor-on-insulator (SOI) structure is provided including an insulating layer and a semiconductor layer formed on the insulating layer and a fuse. The fuse includes a first at least partially silicided raised semiconductor region with a first silicided portion and, adjacent to the first at least partially silicided raised semiconductor region, a second at least partially silicided raised semiconductor region with a second silicided portion. The second silicided portion is formed in direct physical contact with the first silicided portion.

公开(公告)号：US10056481B2

公开(公告)日：2018-08-21

申请号：US15405495

申请日：2017-01-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Christian Schippel ,  Andrei Sidelnicov ,  Gerd Zschaetzsch

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/40

CPC classification number: H01L29/7824 ,  H01L21/28052 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/408 ,  H01L29/4933 ,  H01L29/4983 ,  H01L29/665 ,  H01L29/66689 ,  H01L29/78624 ,  H01L29/78648

Abstract: The present disclosure provides a semiconductor device structure including an active region having a semiconductor-on-insulator (SOI) configuration, a semiconductor device of lateral double-diffused MOS (LDMOS) type, a dual ground plane region formed by two well regions which are counter-doped to each other, the dual ground plane region extending below the semiconductor device, and a deep well region extending below the dual ground plane region. Herein, the semiconductor device of LDMOS type comprises a gate structure formed on the active region, a source region and a drain region formed in the active region at opposing sides of the gate structure, and a channel region and a drift region, both of which being formed in the active region and defining a channel drift junction, wherein the channel drift junction is overlain by the gate structure.

公开(公告)号：US20180090558A1

公开(公告)日：2018-03-29

申请号：US15277583

申请日：2016-09-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alban Zaka ,  Ignasi Cortes Mayol ,  Tom Herrmann ,  Andrei Sidelnicov ,  El Mehdi Bazizi

IPC: H01L49/02 ,  H01L23/535 ,  H01L29/36

CPC classification number: H01L28/60 ,  H01L23/535 ,  H01L29/94

Abstract: A capacitor, such as an N-well capacitor, in a semiconductor device includes a floating semiconductor region, which allows a negative biasing of the channel region of the capacitor while suppressing leakage into the depth of the substrate. In this manner, N-well-based capacitors may be provided in the device level and may have a substantially flat capacitance/voltage characteristic over a moderately wide range of voltages. Consequently, alternating polarity capacitors formed in the metallization system may be replaced by semiconductor-based N-well capacitors.

公开(公告)号：US09905707B1

公开(公告)日：2018-02-27

申请号：US15337026

申请日：2016-10-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andrei Sidelnicov ,  Alban Zaka ,  El Mehdi Bazizi ,  Venkata Naga Ranjith Kumar Nelluri ,  Juergen Faul

IPC: H01L29/00 ,  H01L29/94 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L29/94 ,  H01L21/265 ,  H01L29/66174

Abstract: Capacitive structures in the device level of sophisticated MOS devices may be formed so as to exhibit a significantly reduced capacitance/voltage variability. To this end, a highly doped semiconductor region may be formed in the “channel” of the capacitive structure. For example, for a specified concentration of the dopant species and a specified range of the vertical dimension of the highly doped semiconductor region, a reduced variability of approximately 3% or less may be obtained for a voltage range of, for example, ±5 V.

公开(公告)号：US09627409B2

公开(公告)日：2017-04-18

申请号：US14982112

申请日：2015-12-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Andrei Sidelnicov ,  Maciej Wiatr

IPC: H01L21/76 ,  H01L27/12 ,  H01L49/02 ,  H01L29/786 ,  H01L29/06 ,  H01L21/768 ,  H01L21/762 ,  H01L29/66 ,  H01L21/8258

CPC classification number: H01L27/1207 ,  H01L21/762 ,  H01L21/76805 ,  H01L21/76898 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/0629 ,  H01L28/20 ,  H01L28/24 ,  H01L29/0649 ,  H01L29/66757 ,  H01L29/78603 ,  H01L29/78675

Abstract: A semiconductor device with a metal-containing layer, a first semiconductor layer, that is formed on top of the metal-containing layer, and a resistor that is formed in the metal-containing layer and that is contacted through the first semiconductor layer is provided. Furthermore, a method of manufacturing a semiconductor device is provided, wherein the method comprises manufacturing of a resistor with the following steps: formation of a metal-containing layer over a wafer, particularly a SOI wafer, formation of a first semiconductor layer on top of the metal-containing layer and formation of a contact through the semiconductor layer to the metal-containing layer.

公开(公告)号：US09524962B2

公开(公告)日：2016-12-20

申请号：US14136581

申请日：2013-12-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andrei Sidelnicov ,  Andreas Kurz ,  Alexandru Romanescu

IPC: H01L29/49 ,  H01L23/62 ,  H01L21/285 ,  H01L27/06 ,  H01L23/525 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L27/0629 ,  H01L23/5256 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a semiconductor device including the steps of forming an electrically programmable fuse (e-fuse) on an isolation region and a transistor on an active region of a wafer, wherein forming the transistor includes forming a dummy gate above a substrate, removing the dummy gate and forming a metal gate in place of the dummy gate, and forming the e-fuse includes forming a metal-containing layer above the isolation region, forming a semiconductor layer on the metal-containing layer during the process of forming the dummy gate and of the same material as the dummy gate, forming a hard mask layer on the semiconductor layer formed on the metal-containing layer, and forming contact openings in the hard mask layer and semiconductor layer during the process of removing the dummy gate.

Abstract translation: 一种形成半导体器件的方法，包括以下步骤：在隔离区域上形成电可编程熔丝（e-fuse）和在晶片的有源区上形成晶体管，其中形成晶体管包括在衬底上形成虚拟栅极，去除 虚拟栅极和形成金属栅极代替虚拟栅极，并且形成e熔丝包括在隔离区域上方形成含金属层，在形成虚拟栅极的过程中在含金属层上形成半导体层 栅极和与虚拟栅极相同的材料，在形成在含金属层上的半导体层上形成硬掩模层，并且在去除虚拟栅极的过程中在硬掩模层和半导体层中形成接触开口。

公开(公告)号：US20160300856A1

公开(公告)日：2016-10-13

申请号：US14982112

申请日：2015-12-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Andrei Sidelnicov ,  Maciej Wiatr

IPC: H01L27/12 ,  H01L29/786 ,  H01L23/538 ,  H01L21/8258 ,  H01L21/768 ,  H01L21/762 ,  H01L29/66 ,  H01L49/02 ,  H01L29/06

CPC classification number: H01L27/1207 ,  H01L21/762 ,  H01L21/76805 ,  H01L21/76898 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/0629 ,  H01L28/20 ,  H01L28/24 ,  H01L29/0649 ,  H01L29/66757 ,  H01L29/78603 ,  H01L29/78675

Abstract: A semiconductor device with a metal-containing layer, a first semiconductor layer, that is formed on top of the metal-containing layer, and a resistor that is formed in the metal-containing layer and that is contacted through the first semiconductor layer is provided. Furthermore, a method of manufacturing a semiconductor device is provided, wherein the method comprises manufacturing of a resistor with the following steps: formation of a metal-containing layer over a wafer, particularly a SOI wafer, formation of a first semiconductor layer on top of the metal-containing layer and formation of a contact through the semiconductor layer to the metal-containing layer.

Abstract translation: 提供一种具有含金属层的半导体器件，形成在含金属层顶部的第一半导体层和形成在含金属层中并与第一半导体层接触的电阻器 。 此外，提供了一种制造半导体器件的方法，其中该方法包括制造电阻器，具体步骤如下：在晶片上，特别是SOI晶片上形成含金属层，在第一半导体层上形成第一半导体层 含金属层和通过半导体层形成与含金属层的接触。

公开(公告)号：US10283584B2

公开(公告)日：2019-05-07

申请号：US15277583

申请日：2016-09-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alban Zaka ,  Ignasi Cortes Mayol ,  Tom Herrmann ,  Andrei Sidelnicov ,  El Mehdi Bazizi

IPC: H01L29/78 ,  H01L49/02 ,  H01L23/535 ,  H01L29/94

Abstract: A capacitor, such as an N-well capacitor, in a semiconductor device includes a floating semiconductor region, which allows a negative biasing of the channel region of the capacitor while suppressing leakage into the depth of the substrate. In this manner, N-well-based capacitors may be provided in the device level and may have a substantially flat capacitance/voltage characteristic over a moderately wide range of voltages. Consequently, alternating polarity capacitors formed in the metallization system may be replaced by semiconductor-based N-well capacitors.

公开(公告)号：US20180204944A1

公开(公告)日：2018-07-19

申请号：US15405495

申请日：2017-01-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Christian Schippel ,  Andrei Sidelnicov ,  Gerd Zschaetzsch

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/40

CPC classification number: H01L29/7824 ,  H01L21/28052 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/408 ,  H01L29/4933 ,  H01L29/4983 ,  H01L29/665 ,  H01L29/66689 ,  H01L29/78648

Abstract: The present disclosure provides a semiconductor device structure including an active region having a semiconductor-on-insulator (SOI) configuration, a semiconductor device of lateral double-diffused MOS (LDMOS) type, a dual ground plane region formed by two well regions which are counter-doped to each other, the dual ground plane region extending below the semiconductor device, and a deep well region extending below the dual ground plane region. Herein, the semiconductor device of LDMOS type comprises a gate structure formed on the active region, a source region and a drain region formed in the active region at opposing sides of the gate structure, and a channel region and a drift region, both of which being formed in the active region and defining a channel drift junction, wherein the channel drift junction is overlain by the gate structure.

公开(公告)号：US20170154846A1

公开(公告)日：2017-06-01

申请号：US15428604

申请日：2017-02-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andreas Kurz ,  Andrei Sidelnicov

IPC: H01L23/525 ,  H01L29/08 ,  H01L29/06 ,  H01L27/12 ,  H01L29/78

CPC classification number: H01L23/5256 ,  H01L21/02532 ,  H01L21/76264 ,  H01L21/84 ,  H01L23/53209 ,  H01L27/1203 ,  H01L28/00 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/41783 ,  H01L29/66515 ,  H01L29/66628 ,  H01L29/78 ,  H01L29/7838

Abstract: A semiconductor device with a semiconductor-on-insulator (SOI) structure is provided including an insulating layer and a semiconductor layer formed on the insulating layer and a fuse. The fuse includes a first at least partially silicided raised semiconductor region with a first silicided portion and, adjacent to the first at least partially silicided raised semiconductor region, a second at least partially silicided raised semiconductor region with a second silicided portion. The second silicided portion is formed in direct physical contact with the first silicided portion.