公开(公告)号：US09589807B1

公开(公告)日：2017-03-07

申请号：US15164146

申请日：2016-05-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Haigou Huang ,  Jinping Liu ,  Huang Liu ,  Yuanfang Lu

IPC: H01L21/283 ,  H01L21/762 ,  H01L21/3213 ,  H01L29/66

CPC classification number: H01L21/283 ,  H01L21/32137 ,  H01L21/76224 ,  H01L21/76837 ,  H01L21/7684 ,  H01L29/66545 ,  H01L29/6656

Abstract: A method for eliminating interlayer dielectric (ILD) dishing and controlling gate height uniformity is provided. Embodiments include forming a plurality of polysilicon gates over a substrate, each gate having spacers formed on sides of the polysilicon gates and a nitride cap formed on an upper surface; forming a gapfill material between adjacent polysilicon gates; forming an oxide over the gapfill material between the adjacent polysilicon gates; removing the nitride caps; removing a portion of the oxide between the adjacent polysilicon gates, forming a recess; and forming an ILD cap layer in the recess between the adjacent polysilicon gates.

Abstract translation: 提供消除层间电介质（ILD）凹陷并控制栅极高度均匀性的方法。 实施例包括在衬底上形成多个多晶硅栅极，每个栅极具有形成在多晶硅栅极侧面上的隔离物和形成在上表面上的氮化物盖; 在相邻的多晶硅栅极之间形成间隙填充材料; 在相邻的多晶硅栅极之间的间隙填充材料上形成氧化物; 去除氮化物盖; 去除相邻多晶硅栅极之间的氧化物的一部分，形成凹陷; 以及在相邻的多晶硅栅极之间的凹槽中形成ILD覆盖层。