公开(公告)号：US12122120B2

公开(公告)日：2024-10-22

申请号：US17521170

申请日：2021-11-08

Applicant: The Research Foundation for The State University of new York

Inventor： Scott N. Schiffres ,  Arad Azizi

IPC: F28F7/00 ,  B22F10/28 ,  B23K26/342 ,  B32B7/12 ,  B32B15/01 ,  B33Y10/00 ,  B33Y70/10 ,  B33Y80/00 ,  F28D15/00 ,  F28F21/00 ,  F28F21/02 ,  F28F21/04 ,  F28F21/08 ,  H01L21/283 ,  H01L23/367 ,  H01L23/373 ,  B22F10/36

CPC classification number: B32B15/01 ,  B22F10/28 ,  B23K26/342 ,  B32B7/12 ,  B33Y10/00 ,  B33Y70/10 ,  B33Y80/00 ,  F28D15/00 ,  F28F21/006 ,  F28F21/02 ,  F28F21/04 ,  F28F21/081 ,  H01L21/283 ,  H01L23/367 ,  H01L23/3735 ,  B22F10/36 ,  B32B2457/00 ,  F28F2210/00 ,  B22F2999/00 ,  B22F7/08 ,  B22F10/28

Abstract: A technique to additively print onto a dissimilar material, especially ceramics and glasses (e.g., semiconductors, graphite, diamond, other metals) is disclosed herein. The technique enables manufacture of heat removal devices and other deposited structures, especially on heat sensitive substrates. It also enables novel composites through additive manufacturing. The process enables rapid bonding, orders-of-magnitude faster than conventional techniques.

公开(公告)号：US20240222140A1

公开(公告)日：2024-07-04

申请号：US18393823

申请日：2023-12-22

Applicant: Phoenix Pioneer Technology Co., Ltd.

Inventor： Che-Wei HSU ,  Pao-Hung CHOU ,  Shih-Ping HSU

IPC: H01L21/48 ,  H01L21/283 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L21/4857 ,  H01L21/283 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/29 ,  H01L24/73 ,  H01L2224/13025 ,  H01L2224/13147 ,  H01L2224/29009 ,  H01L2224/29025 ,  H01L2224/73103 ,  H01L2924/18162

Abstract: A package carrier board includes a first circuit build-up structure, a patterned magnetic conductive metal layer, a plurality of first conductive pillar, a second insulating layer, and a second circuit build-up structure. The patterned magnetic conductive metal layer is disposed above the first circuit build-up structure, and the cross-sectional pattern of the patterned magnetic conductive metal layer is L-shaped and/or U-shaped. The first conductive pillars are disposed on the first circuit build-up structure and located outside of the patterned magnetic conductive metal layer. The second insulating layer covers the patterned magnetic conductive metal layer and the first conductive pillars. The second circuit build-up structure is disposed on the second insulating layer. The first circuit build-up structure, the first conductive pillars, the second insulating layer, and the second circuit build-up structure are combined to form an inductive circuit structure. Additionally, a manufacturing method for the package carrier board is also disclosed.

公开(公告)号：US20240194486A1

公开(公告)日：2024-06-13

申请号：US18444826

申请日：2024-02-19

Applicant: NXP B.V.

Inventor： Kuan-Hsiang Mao ,  Wen Hung Huang ,  Che Ming Fang ,  Yufu Liu

IPC: H01L21/283 ,  H01L21/78 ,  H01L23/00

CPC classification number: H01L21/283 ,  H01L21/78 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/05558 ,  H01L2924/3511

Abstract: A method for forming a packaged integrated circuit device includes providing a semiconductor wafer having a plurality of integrated circuit devices, each integrated circuit device extending into the semiconductor wafer to a first depth, and grinding a backside of the silicon wafer to no more than the first depth. The method further includes forming a backside cut between the integrated circuit devices. The backside cut extends to within the first depth, but the backside cut does not extend completely through the semiconductor wafer. The backside cut exposes a plurality of edges of each of the integrated circuit devices. The method further includes depositing, on the backside of the wafer, a metallization layer on a bottom surface of the integrated circuit devices and on the edges.

公开(公告)号：US20240113157A1

公开(公告)日：2024-04-04

申请号：US18374205

申请日：2023-09-28

Applicant: Semiconductor Manufacturing International (Shanghai) Corporation

Inventor： Jisong JIN

IPC: H01L21/283 ,  H01L21/3213

CPC classification number: H01L28/60 ,  H01L21/283 ,  H01L21/3213

Abstract: A semiconductor structure includes a substrate that includes a first region, a second region, and a third region; a first electrode layer disposed over the first region and the second region; a first dielectric layer disposed over the substrate; a second electrode layer disposed on the first dielectric layer over the third region and the second region; a second dielectric layer disposed over the substrate; a third electrode layer disposed on the second dielectric layer over the second region and over a portion of each of the third and first regions; and a first plug disposed over the first region and a second plug disposed over the third region. The first plug is electrically connected with one of the first, second and third electrode layers, and the second plug is electrically connected with the other two electrode layers.

公开(公告)号：US11916129B2

公开(公告)日：2024-02-27

申请号：US17348718

申请日：2021-06-15

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  Chandra Mouli

IPC: H01L29/66 ,  B82Y10/00 ,  H01L29/06 ,  H01L29/417 ,  H10N70/00 ,  H01L29/08 ,  H01L29/872 ,  H01L21/28 ,  H01L21/283 ,  H01L29/88 ,  H01L49/02

CPC classification number: H01L29/66151 ,  B82Y10/00 ,  H01L21/28 ,  H01L21/283 ,  H01L29/068 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66143 ,  H01L29/872 ,  H01L29/88 ,  H10N70/00 ,  H01L28/90

Abstract: Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is deposited along an undulating topography that extends across the pedestal and base, and a second electrode is formed over the least one layer. The first electrode, at least one layer, and second electrode together form a structure that conducts current between the first and second electrodes when voltage of one polarity is applied to the structure, and that inhibits current flow between the first and second electrodes when voltage having a polarity opposite to said one polarity is applied to the structure. Some embodiments include diodes having a first electrode that contains two or more projections extending upwardly from a base, having at least one layer over the first electrode, and having a second electrode over the at least one layer.

公开(公告)号：US20240056074A1

公开(公告)日：2024-02-15

申请号：US18496909

申请日：2023-10-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： TZUNG-YO HUNG ,  PIN-DAI SUE ,  CHIEN-CHI TIEN ,  TING-WEI CHIANG

IPC: H03K17/687 ,  H03K19/0948 ,  G05F3/16 ,  H03K19/0185 ,  H01L21/02 ,  H01L21/283 ,  H01L21/822 ,  H01L29/423 ,  H01L29/06

CPC classification number: H03K17/6872 ,  H03K19/0948 ,  G05F3/16 ,  H03K19/018571 ,  H01L21/02104 ,  H01L21/283 ,  H01L21/822 ,  H01L29/42312 ,  H01L29/0669 ,  B82Y10/00

Abstract: An integrated circuit device includes: an integrated circuit module; a first field-effect transistor coupled between the integrated circuit module and a first reference voltage, and controlled by a first control signal; and a second field-effect transistor coupled between the integrated circuit module and the first reference voltage; wherein the second field-effect transistor is a complementary field-effect transistor of the first field-effect transistor, and the first field-effect transistor and the second field-effect transistor are configured to generate a second reference voltage for the integrated circuit module according to the first control signal.

公开(公告)号：US11855085B2

公开(公告)日：2023-12-26

申请号：US17872417

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chang Hung ,  Chia-Jen Chen ,  Ming-Ching Chang ,  Shu-Yuan Ku ,  Yi-Hsuan Hsiao ,  I-Wei Yang

IPC: H01L27/088 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L21/283 ,  H01L29/78 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/321

CPC classification number: H01L27/0886 ,  H01L21/283 ,  H01L21/31116 ,  H01L21/32136 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/42376 ,  H01L29/49 ,  H01L29/4991 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/78 ,  H01L21/02068 ,  H01L21/31053 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/32139 ,  H01L29/6656

Abstract: Methods of cutting gate structures, and structures formed, are described. In an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. The first and second gate structures extend parallel. The active area includes a source/drain region disposed laterally between the first and second gate structures. The gate cut-fill structure has first and second primary portions and an intermediate portion. The first and second primary portions abut the first and second gate structures, respectively. The intermediate portion extends laterally between the first and second primary portions. First and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.

公开(公告)号：US11804533B2

公开(公告)日：2023-10-31

申请号：US18173541

申请日：2023-02-23

Applicant: Acorn Semi, LLC

Inventor： Walter A. Harrison ,  Paul A. Clifton ,  Andreas Goebel ,  R. Stockton Gaines

IPC: H01L29/47 ,  H01L21/285 ,  H01L29/04 ,  H01L21/283 ,  H01L29/45 ,  H01L21/324 ,  H01L29/161

CPC classification number: H01L29/47 ,  H01L21/283 ,  H01L21/28512 ,  H01L21/28518 ,  H01L21/324 ,  H01L29/045 ,  H01L29/161 ,  H01L29/456

Abstract: Techniques for reducing the specific contact resistance of metal-semiconductor (group IV) junctions by interposing a monolayer of group V or group III atoms at the interface between the metal and the semiconductor, or interposing a bi-layer made of one monolayer of each, or interposing multiple such bi-layers. The resulting low specific resistance metal-group IV semiconductor junctions find application as a low resistance electrode in semiconductor devices including electronic devices (e.g., transistors, diodes, etc.) and optoelectronic devices (e.g., lasers, solar cells, photodetectors, etc.) and/or as a metal source and/or drain region (or a portion thereof) in a field effect transistor (FET). The monolayers of group III and group V atoms are predominantly ordered layers of atoms formed on the surface of the group IV semiconductor and chemically bonded to the surface atoms of the group IV semiconductor.

公开(公告)号：US11798996B2

公开(公告)日：2023-10-24

申请号：US17813822

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Ming Lee ,  Wei-Yang Lee

IPC: H01L29/40 ,  H01L21/283 ,  H01L29/417 ,  H01L29/66 ,  H01L29/786 ,  H01L21/3213

CPC classification number: H01L29/401 ,  H01L21/283 ,  H01L21/32135 ,  H01L29/4175 ,  H01L29/66795 ,  H01L29/78696

Abstract: A method includes performing a first etching process on a backside of a substrate to expose a dummy contact structure, performing a first deposition process to deposit a first dielectric layer around the dummy contract structure, performing a second deposition process to deposit an oxide layer on the first dielectric layer, removing the dummy contract structure to form a trench, depositing a sacrificial layer on sidewalls of the trench, depositing a second dielectric layer on the sacrificial layer, filling the trench with a conductive material, and removing the sacrificial layer to form an air spacer between the first dielectric layer and the second dielectric layer.

公开(公告)号：US20190051826A1

公开(公告)日：2019-02-14

申请号：US16164510

申请日：2018-10-18

Applicant: Micron Technology, Inc.

Inventor： Thomas R. Omstead ,  Cole S. Franklin

IPC: H01L45/00 ,  C23C16/36 ,  C23C16/455 ,  H01L21/02 ,  C23C16/34 ,  H01L27/24 ,  H01L21/283 ,  H01L21/768

CPC classification number: H01L45/124 ,  C23C16/345 ,  C23C16/36 ,  C23C16/45534 ,  C23C16/45542 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02315 ,  H01L21/283 ,  H01L21/76829 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/065 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/141 ,  H01L45/16

Abstract: A method of forming a silicon-containing dielectric material. The method includes forming a plasma comprising nitrogen radicals, absorbing the nitrogen radicals onto a substrate, and exposing the substrate to a silicon-containing precursor in a non-plasma environment to form monolayers of a silicon-containing dielectric material on the substrate. Additional methods are also described, as are semiconductor device structures including the silicon-containing dielectric material and methods of forming the semiconductor device structures.