公开(公告)号：US10395987B2

公开(公告)日：2019-08-27

申请号：US15402150

申请日：2017-01-09

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Chia Ching Yeo ,  Kiok Boone Elgin Quek ,  Khee Yong Lim ,  Jae Han Cha ,  Yung Fu Chong

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

Abstract: The disclosure is related to MV transistors with reduced gate induced drain leakage (GIDL) and impact ionization. The reduced GILD and impact ionization are achieved without increasing device pitch of the MV transistor. A low voltage (LV) device region and a medium voltage (MV) device region are disposed on the substrate. Non-extended spacers are disposed on the sidewalls of the LV gate in the LV device region; extended L shaped spacers are disposed on the sidewalls of the MV gate in the MV device region. The non-extended spacers and extended L shape spacers are patterned simultaneously. Extended L shaped spacers displace the MV heavily doped (HD) regions a greater distance from at least one sidewall of the MV gate to reduce the GIDL and impact ionization of the MV transistor.

公开(公告)号：US09653365B1

公开(公告)日：2017-05-16

申请号：US15093888

申请日：2016-04-08

Applicant: Globalfoundries Singapore Pte. Ltd.

Inventor： Khee Yong Lim ,  Jae Han Cha ,  Chia Ching Yeo ,  Kiok Boone Elgin Quek

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/8234

CPC classification number: H01L21/84 ,  H01L21/823418 ,  H01L21/823481 ,  H01L27/1207

Abstract: A method for fabricating an integrated circuit that include providing or obtaining an extremely thin silicon-on-insulator (ETSOI) substrate, dividing the ETSOI substrate into a low voltage field effect transistor (FET) region and one or both of a medium voltage FET region and a high voltage FET regions, and forming a low voltage FET within the low voltage FET regions and forming a medium and/or high voltage FET within the medium and/or high voltage FET region(s). Channel, source, and drain structures of the low voltage FET are formed in an upper silicon layer that is disposed above a buried oxide layer of the ETSOI substrate, whereas channel, source, and drain structures of the medium and/or high voltage FETs are formed at least partially below the upper silicon layer.