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    Memory arrays and methods of forming the same
    6.
    发明授权
    Memory arrays and methods of forming the same 有权

    公开(公告)号：US10762966B2

    公开(公告)日：2020-09-01

    申请号：US16174318

    申请日：2018-10-30

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Xinshu Cai ,  Shyue Seng Tan ,  Kiok Boone Elgin Quek

    IPC: G11C11/34 ,  G11C16/10 ,  G11C16/14 ,  G11C16/04 ,  H01L27/11521

    Abstract: A device having at least one memory cell over a substrate is provided. The at least one memory cell includes a source region and a drain region in the substrate, and a first gate and a second gate over the substrate. The first and second gates are arranged between the source region and the drain region. The first and second gate are separated by an intergate dielectric. The first gate is configured as a select gate and erase gate of the at least one memory cell, and the second gate is configured as a storage gate of the at least one memory cell. The second gate comprises a floating gate and a control gate over the floating gate. The device further includes source/drain (S/D) contacts extending from the source region and the drain region. The source region and the drain region are coupled to either one of a source line (SL) or a bit line (BL) through the S/D contacts.

    Integrated circuits with sensors and methods for producing the same
    7.
    发明授权
    Integrated circuits with sensors and methods for producing the same 有权

    公开(公告)号：US10746694B2

    公开(公告)日：2020-08-18

    申请号：US16203769

    申请日：2018-11-29

    Applicant: Globalfoundries Singapore Pte. Ltd.

    Inventor： Eng Huat Toh ,  Bin Liu ,  Shyue Seng Tan ,  Kiok Boone Elgin Quek

    IPC: H01L27/12 ,  G01N27/414

    Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a detection layer, a substrate, and a transistor having a transistor gate electrode, a transistor source, and a transistor drain. A capacitor gate electrode overlies the substrate, where the capacitor gate electrode and the transistor gate electrode are electrically connected with each other and with the detection layer. A capacitor well is defined within the substrate, and a gate insulator is positioned between the capacitor well and the capacitor gate electrode. A capacitor includes the capacitor gate electrode, the gate insulator, and the capacitor well.

    Selective shielding of ambient light at chip level
    8.
    发明授权
    Selective shielding of ambient light at chip level 有权

    公开(公告)号：US10707358B2

    公开(公告)日：2020-07-07

    申请号：US16027363

    申请日：2018-07-04

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Wanbing Yi ,  Juan Boon Tan ,  Kiok Boone Elgin Quek ,  Khee Yong Lim ,  Chim Seng Seet ,  Rajesh Nair

    IPC: H01L31/0216 ,  H01L23/00

    Abstract: A semiconductor device having a substrate with at least one photo-detecting region and at least one bond pad is provided. A first passivation layer is deposited over the substrate and over step portions at the edges of the bond pad and a trench having sidewalls and a bottom surface is formed in the substrate. A light shielding layer is deposited over the first passivation layer and covering the trench sidewalls. The light shielding layer has end portions at the photo-detecting region, at step portions at the edges of the bond pad and at the bottom surface of the trench. A second passivation layer is deposited over the light shielding layer. A third passivation layer is deposited over the end portions of the light shielding layer at the photo-detecting region and at the step portions at edges of the bond pad.

    Reduced capacitance coupling effects in devices
    9.
    发明授权
    Reduced capacitance coupling effects in devices 有权

    公开(公告)号：US10374052B2

    公开(公告)日：2019-08-06

    申请号：US15730745

    申请日：2017-10-12

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Shyue Seng Tan ,  Kiok Boone Elgin Quek ,  Eng Huat Toh

    IPC: H01L29/49 ,  H01L23/535 ,  H01L29/51 ,  H01L29/78 ,  H01L23/522 ,  H01L21/28 ,  H01L29/66

    Abstract: A semiconductor device with reduce capacitance coupling effect which can reduce the overall parasitic capacitances is disclosed. The semiconductor device includes a gate sidewall spacer with a negative capacitance dielectric layer with and without a dielectric layer. The semiconductor device may also include a plurality of interlevel dielectric (ILD) with a layer of negative capacitance dielectric layer followed by a dielectric layer disposed in-between metal lines in any ILD and combinations. The negative capacitance dielectric layer includes a ferroelectric material which has calculated and selected thicknesses with desired negative capacitance to provide optimal total overlap capacitance in the circuit component which aims to reduce the overall capacitance coupling effect.

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