公开(公告)号：US11444168B2

公开(公告)日：2022-09-13

申请号：US17086501

申请日：2020-11-02

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Jiacheng Lei ,  James Jerry Joseph ,  Khee Yong Lim ,  Lulu Peng ,  Lawrence Selvaraj Susai

IPC: H01L29/423 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778 ,  H01L29/10

Abstract: A transistor device may be provided, including a substrate; a buffer layer arranged over the substrate; a source terminal, a drain terminal, and a gate terminal arranged over the buffer layer; a barrier layer arranged over the buffer layer; and a passivation layer arranged over the barrier layer. The gate terminal may be arranged laterally between the source terminal and the drain terminal, the barrier layer may include a recess laterally between the gate terminal and the drain terminal, a part of the gate terminal may be arranged over the passivation layer and the passivation layer may extend into the recess of the barrier layer.

公开(公告)号：US11824125B2

公开(公告)日：2023-11-21

申请号：US17511569

申请日：2021-10-27

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Sagar Premnath Karalkar ,  James Jerry Joseph ,  Jie Zeng ,  Milova Paul ,  Kyong Jin Hwang

IPC: H01L29/861 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/861 ,  H01L29/0684 ,  H01L29/66121

Abstract: An electrostatic discharge (ESD) protection device is provided. The ESD protection device includes a substrate, an active region, a first terminal region, and a second terminal region. The substrate includes dopants having a first dopant conductivity. The active region is arranged over the substrate and has an upper surface. The first terminal region and the second terminal region are arranged in the active region laterally spaced apart from each other. The first terminal region and the second terminal region each include a well region having dopants of the first dopant conductivity and a first doped region arranged in the well region. The first doped region includes dopants having a second dopant conductivity.

公开(公告)号：US11901445B2

公开(公告)日：2024-02-13

申请号：US17097012

申请日：2020-11-13

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Jiacheng Lei ,  James Jerry Joseph ,  Lawrence Selvaraj Susai ,  Shyue Seng Tan

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/7786 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/42316 ,  H01L29/66462

Abstract: A transistor may include a buffer layer, source and drain contacts on the buffer layer, a barrier layer on the buffer layer, a conductive member on the barrier layer, a dielectric stack, and a gate metal. The barrier layer may be between the source and drain contacts. The conductive member may include a p-doped III-V compound. The dielectric stack may be on the barrier layer and on the conductive member. The dielectric stack may include a first dielectric layer and a second dielectric layer on the first dielectric layer. First and second trenches may extend through the dielectric stack to the conductive member and to the first dielectric layer, respectively. The gate metal may be on the dielectric stack, and may contact the conductive member through the first trench and may contact the first dielectric layer through the second trench.