公开(公告)号：US20210327487A1

公开(公告)日：2021-10-21

申请号：US17365481

申请日：2021-07-01

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Amogh AGRAWAL ,  Ajey Poovannummoottil JACOB ,  Bipul C. PAUL

IPC: G11C11/16

Abstract: The present disclosure relates to a structure including a non-fixed read-cell circuit configured to switch from a first state to a second state based on a state of a memory cell to generate a sensing margin.

公开(公告)号：US20210090627A1

公开(公告)日：2021-03-25

申请号：US16582474

申请日：2019-09-25

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Anuj GUPTA ,  Bipul C. PAUL ,  Joseph VERSAGGI

IPC: G11C11/16

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to twisted wordline structures and methods of manufacture. The memory array structure includes: a plurality of bitcells comprising memory elements and access transistors; a plurality of bitlines and wordlines which interconnect the bitcells; a plurality of dummy bitcells which intersect with the bitlines and wordlines; and a plurality of twisted wordline strap cells which twist wordlines in the dummy bitcells and connect a higher metal layer in the bitcells to a gate structure of the access transistor.

公开(公告)号：US20220180923A1

公开(公告)日：2022-06-09

申请号：US17110674

申请日：2020-12-03

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Akhilesh R. JAISWAL ,  Bipul C. PAUL ,  Steven R. SOSS

IPC: G11C11/412 ,  G11C11/419

Abstract: The present disclosure relates to a structure including a latch circuit, a first non-volatile field effect transistor (FET) connecting to a first side of the latch circuit and a bit line, and a second non-volatile field effect transistor (FET) connecting to a second side of the latch circuit and a complementary bit line.