公开(公告)号：US11158624B1

公开(公告)日：2021-10-26

申请号：US16857298

申请日：2020-04-24

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Wenjun Li ,  Chen Perkins Yan ,  Tamilmani Ethirajan ,  Cole E. Zemke

IPC: H01L27/08 ,  H01L27/02 ,  H01L27/088 ,  H01L29/08 ,  H01L29/423 ,  H01L21/8234 ,  H03F3/195 ,  H01L27/12

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to unitary Cascode cells with resistance and capacitance optimization, and methods of manufacture. The structure includes a common source FET (CS-FET) in a first portion of a single common semiconductor region, the CS-FET comprising a source region and a drain region, a common gate FET (CG-FET) in a second portion of the single common semiconductor region, the CG-FET comprising a source region and a drain region, and a doped connecting region of the single common semiconductor region, connecting the drain of the CS-FET and the source of the CG-FET.