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1.
公开(公告)号:US11362177B2
公开(公告)日:2022-06-14
申请号:US16774157
申请日:2020-01-28
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Arkadiusz Malinowski , Baofu Zhu , Frank W. Mont , Ali Razavieh , Julien Frougier
Abstract: One illustrative transistor of a first dopant type disclosed herein includes a gate structure positioned above a semiconductor substrate and first and second overall epitaxial cavities formed in the semiconductor substrate on opposite sides of the gate structure. The device also includes a counter-doped epitaxial semiconductor material positioned proximate a bottom of each of the first and second overall epitaxial cavities, wherein the counter-doped epitaxial semiconductor material is doped with a second dopant type that is opposite to the first dopant type, and a same-doped epitaxial semiconductor material positioned in each of the first and second overall epitaxial cavities above the counter-doped epitaxial semiconductor material, wherein the same-doped epitaxial semiconductor material is doped with a dopant of the first dopant type.
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2.
公开(公告)号:US11205699B2
公开(公告)日:2021-12-21
申请号:US16655429
申请日:2019-10-17
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Arkadiusz Malinowski , Baofu Zhu , Frank W. Mont , Julien Frougier , Ali Razavieh
Abstract: One illustrative transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate and first and second overall epitaxial cavities formed in the semiconductor substrate on opposite sides of the gate structure. In one embodiment, each of the first and second overall epitaxial cavities includes a substantially vertically oriented upper epitaxial cavity and a lower epitaxial cavity, wherein the substantially vertically oriented upper epitaxial cavity extends from an upper surface of the semiconductor substrate to the lower epitaxial cavity. A lateral width of the lower epitaxial cavity is greater than a lateral width of the upper epitaxial cavity. The device also includes epitaxial semiconductor material positioned in each of the first and second overall epitaxial cavities.
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3.
公开(公告)号:US20210118993A1
公开(公告)日:2021-04-22
申请号:US16655429
申请日:2019-10-17
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Arkadiusz Malinowski , Baofu Zhu , Frank W. Mont , Julien Frougier , Ali Razavieh
Abstract: One illustrative transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate and first and second overall epitaxial cavities formed in the semiconductor substrate on opposite sides of the gate structure. In one embodiment, each of the first and second overall epitaxial cavities includes a substantially vertically oriented upper epitaxial cavity and a lower epitaxial cavity, wherein the substantially vertically oriented upper epitaxial cavity extends from an upper surface of the semiconductor substrate to the lower epitaxial cavity. A lateral width of the lower epitaxial cavity is greater than a lateral width of the upper epitaxial cavity. The device also includes epitaxial semiconductor material positioned in each of the first and second overall epitaxial cavities.
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公开(公告)号:US11610839B2
公开(公告)日:2023-03-21
申请号:US16666808
申请日:2019-10-29
Applicant: GLOBALFOUNDRIES U.S. INC.
Inventor: Tung-Hsing Lee , Teng-Yin Lin , Frank W. Mont , Edward J. Gordon , Asmaa Elkadi , Alexander Martin , Won Suk Lee , Anvitha Shampur
IPC: H01L23/522 , H01L49/02 , H01F27/28 , H01F27/24 , H01F41/04
Abstract: The present disclosure relates to semiconductor structures and, more particularly, to dummy fill structures and methods of manufacture. The structure includes: a passive device formed in interlevel dielectric material; and a plurality of metal dummy fill structures composed of at least one main branch and two extending legs from at least one side of the main branch, the at least two extending legs being positioned and structured to suppress eddy currents of the passive device.
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5.
公开(公告)号:US20210233999A1
公开(公告)日:2021-07-29
申请号:US16774157
申请日:2020-01-28
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Arkadiusz Malinowski , Baofu Zhu , Frank W. Mont , Ali Razavieh , Julien Frougier
Abstract: One illustrative transistor of a first dopant type disclosed herein includes a gate structure positioned above a semiconductor substrate and first and second overall epitaxial cavities formed in the semiconductor substrate on opposite sides of the gate structure. The device also includes a counter-doped epitaxial semiconductor material positioned proximate a bottom of each of the first and second overall epitaxial cavities, wherein the counter-doped epitaxial semiconductor material is doped with a second dopant type that is opposite to the first dopant type, and a same-doped epitaxial semiconductor material positioned in each of the first and second overall epitaxial cavities above the counter-doped epitaxial semiconductor material, wherein the same-doped epitaxial semiconductor material is doped with a dopant of the first dopant type.
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