公开(公告)号：US11094822B1

公开(公告)日：2021-08-17

申请号：US16751380

申请日：2020-01-24

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Arkadiusz Malinowski ,  Baofu Zhu ,  Judson R. Holt ,  Shiv Kumar Mishra

IPC: H01L29/76 ,  H01L21/84 ,  H01L29/80 ,  H01L29/78 ,  H01L27/12 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L29/10

Abstract: One illustrative transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate and first and second overall cavities formed in the semiconductor substrate on opposite sides of the gate structure. In this example, each of the first and second overall cavities comprise a substantially vertically oriented upper epitaxial cavity and a lower insulation cavity, wherein the substantially vertically oriented upper epitaxial cavity extends from an upper surface of the semiconductor substrate to the lower insulation cavity. The transistor also includes an insulation material positioned in at least a portion of the lower insulation cavity of each of the first and second overall cavities and epitaxial semiconductor material positioned in at least the substantially vertically oriented upper epitaxial cavity of each of the first and second overall cavities.

公开(公告)号：US11239315B2

公开(公告)日：2022-02-01

申请号：US16780494

申请日：2020-02-03

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Shiv Kumar Mishra ,  Baofu Zhu ,  Arkadiusz Malinowski ,  Kaushikee Mishra

IPC: H01L29/06 ,  H01L21/26 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L21/266 ,  H01L21/74 ,  H01L21/762 ,  H01L21/265

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to dual trench isolation structures and methods of manufacture. The structure includes: a doped well region in a substrate; a dual trench isolation region within the doped well region, the dual trench isolation region comprising a first isolation region of a first depth and a second isolation region of a second depth, different than the first depth; and a gate structure on the substrate and extending over a portion of the dual trench isolation region.

公开(公告)号：US20210234045A1

公开(公告)日：2021-07-29

申请号：US16751380

申请日：2020-01-24

Applicant: GLOBALFOUNDRIES U.S, Inc.

Inventor： Arkadiusz Malinowski ,  Baofu Zhu ,  Judson R. Holt ,  Shiv Kumar Mishra

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L21/02

Abstract: One illustrative transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate and first and second overall cavities formed in the semiconductor substrate on opposite sides of the gate structure. In this example, each of the first and second overall cavities comprise a substantially vertically oriented upper epitaxial cavity and a lower insulation cavity, wherein the substantially vertically oriented upper epitaxial cavity extends from an upper surface of the semiconductor substrate to the lower insulation cavity. The transistor also includes an insulation material positioned in at least a portion of the lower insulation cavity of each of the first and second overall cavities and epitaxial semiconductor material positioned in at least the substantially vertically oriented upper epitaxial cavity of each of the first and second overall cavities.