公开(公告)号：US11362178B2

公开(公告)日：2022-06-14

申请号：US16676488

申请日：2019-11-07

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Jiehui Shu ,  Rinus Tek Po Lee ,  Baofu Zhu

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/423 ,  H01L27/088

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to asymmetric source and drain structures and methods of manufacture. The structure includes: at least one gate structure; a straight spacer adjacent to the at least one gate structure; and an L-shaped spacer on a side of the at least one gate structure opposing the straight spacer, the L-shaped spacer extending a first diffusion region further away from the at least one gate structure than the straight spacer extends a second diffusion region on a second side away from the at least one gate structure.

公开(公告)号：US11177385B2

公开(公告)日：2021-11-16

申请号：US16781236

申请日：2020-02-04

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Haiting Wang ,  Sipeng Gu ,  Jiehui Shu ,  Baofu Zhu

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure extends over a channel region in a semiconductor body. The gate structure has a first side surface and a second side surface opposite the first side surface. A first source/drain region is positioned adjacent to the first side surface of the gate structure and a second source/drain region is positioned adjacent to the second side surface of the gate structure. The first source/drain region includes a first epitaxial semiconductor layer, and the second source/drain region includes a second epitaxial semiconductor layer. A first top surface of the first epitaxial semiconductor layer is positioned at a first distance from the channel region, a second top surface of the second epitaxial semiconductor layer is positioned at a second distance from the channel region, and the first distance is greater than the second distance.

公开(公告)号：US11362177B2

公开(公告)日：2022-06-14

申请号：US16774157

申请日：2020-01-28

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Arkadiusz Malinowski ,  Baofu Zhu ,  Frank W. Mont ,  Ali Razavieh ,  Julien Frougier

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/78

Abstract: One illustrative transistor of a first dopant type disclosed herein includes a gate structure positioned above a semiconductor substrate and first and second overall epitaxial cavities formed in the semiconductor substrate on opposite sides of the gate structure. The device also includes a counter-doped epitaxial semiconductor material positioned proximate a bottom of each of the first and second overall epitaxial cavities, wherein the counter-doped epitaxial semiconductor material is doped with a second dopant type that is opposite to the first dopant type, and a same-doped epitaxial semiconductor material positioned in each of the first and second overall epitaxial cavities above the counter-doped epitaxial semiconductor material, wherein the same-doped epitaxial semiconductor material is doped with a dopant of the first dopant type.

公开(公告)号：US11205699B2

公开(公告)日：2021-12-21

申请号：US16655429

申请日：2019-10-17

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Arkadiusz Malinowski ,  Baofu Zhu ,  Frank W. Mont ,  Julien Frougier ,  Ali Razavieh

IPC: H01L29/08 ,  H01L29/78

Abstract: One illustrative transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate and first and second overall epitaxial cavities formed in the semiconductor substrate on opposite sides of the gate structure. In one embodiment, each of the first and second overall epitaxial cavities includes a substantially vertically oriented upper epitaxial cavity and a lower epitaxial cavity, wherein the substantially vertically oriented upper epitaxial cavity extends from an upper surface of the semiconductor substrate to the lower epitaxial cavity. A lateral width of the lower epitaxial cavity is greater than a lateral width of the upper epitaxial cavity. The device also includes epitaxial semiconductor material positioned in each of the first and second overall epitaxial cavities.

公开(公告)号：US11094822B1

公开(公告)日：2021-08-17

申请号：US16751380

申请日：2020-01-24

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Arkadiusz Malinowski ,  Baofu Zhu ,  Judson R. Holt ,  Shiv Kumar Mishra

IPC: H01L29/76 ,  H01L21/84 ,  H01L29/80 ,  H01L29/78 ,  H01L27/12 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L29/10

Abstract: One illustrative transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate and first and second overall cavities formed in the semiconductor substrate on opposite sides of the gate structure. In this example, each of the first and second overall cavities comprise a substantially vertically oriented upper epitaxial cavity and a lower insulation cavity, wherein the substantially vertically oriented upper epitaxial cavity extends from an upper surface of the semiconductor substrate to the lower insulation cavity. The transistor also includes an insulation material positioned in at least a portion of the lower insulation cavity of each of the first and second overall cavities and epitaxial semiconductor material positioned in at least the substantially vertically oriented upper epitaxial cavity of each of the first and second overall cavities.

公开(公告)号：US11563085B2

公开(公告)日：2023-01-24

申请号：US17243832

申请日：2021-04-29

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Jiehui Shu ,  Baofu Zhu ,  Haiting Wang ,  Sipeng Gu

IPC: H01L29/08 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/78

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure is arranged over a channel region of a semiconductor body. A first source/drain region is coupled to a first portion of the semiconductor body, and a second source/drain region is located in a second portion the semiconductor body. The first source/drain region includes an epitaxial semiconductor layer containing a first concentration of a dopant. The second source/drain region contains a second concentration of the dopant. The channel region is positioned in the semiconductor body between the first source/drain region and the second source/drain region.

公开(公告)号：US20210234045A1

公开(公告)日：2021-07-29

申请号：US16751380

申请日：2020-01-24

Applicant: GLOBALFOUNDRIES U.S, Inc.

Inventor： Arkadiusz Malinowski ,  Baofu Zhu ,  Judson R. Holt ,  Shiv Kumar Mishra

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L21/02

Abstract: One illustrative transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate and first and second overall cavities formed in the semiconductor substrate on opposite sides of the gate structure. In this example, each of the first and second overall cavities comprise a substantially vertically oriented upper epitaxial cavity and a lower insulation cavity, wherein the substantially vertically oriented upper epitaxial cavity extends from an upper surface of the semiconductor substrate to the lower insulation cavity. The transistor also includes an insulation material positioned in at least a portion of the lower insulation cavity of each of the first and second overall cavities and epitaxial semiconductor material positioned in at least the substantially vertically oriented upper epitaxial cavity of each of the first and second overall cavities.

公开(公告)号：US20210233999A1

公开(公告)日：2021-07-29

申请号：US16774157

申请日：2020-01-28

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Arkadiusz Malinowski ,  Baofu Zhu ,  Frank W. Mont ,  Ali Razavieh ,  Julien Frougier

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/06

Abstract: One illustrative transistor of a first dopant type disclosed herein includes a gate structure positioned above a semiconductor substrate and first and second overall epitaxial cavities formed in the semiconductor substrate on opposite sides of the gate structure. The device also includes a counter-doped epitaxial semiconductor material positioned proximate a bottom of each of the first and second overall epitaxial cavities, wherein the counter-doped epitaxial semiconductor material is doped with a second dopant type that is opposite to the first dopant type, and a same-doped epitaxial semiconductor material positioned in each of the first and second overall epitaxial cavities above the counter-doped epitaxial semiconductor material, wherein the same-doped epitaxial semiconductor material is doped with a dopant of the first dopant type.

公开(公告)号：US10985244B2

公开(公告)日：2021-04-20

申请号：US16451797

申请日：2019-06-25

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Shesh Mani Pandey ,  Chung Foong Tan ,  Baofu Zhu

IPC: H01L29/06 ,  H01L21/762 ,  H01L27/12

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to n-well resistors and methods of manufacture. The structure includes: a substrate composed of a N-well implant region and a deep N-well implant region; and a plurality of shallow trench isolation regions extending into both the N-well implant region and a deep N-well implant region.

公开(公告)号：US11239366B2

公开(公告)日：2022-02-01

申请号：US16776938

申请日：2020-01-30

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Wenjun Li ,  Man Gu ,  Baofu Zhu

IPC: H01L21/336 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/08

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure extends over a semiconductor body, a first source/drain region includes an epitaxial semiconductor layer on a first portion of the semiconductor body, and a second source/drain region is positioned in a second portion of the semiconductor body. The gate structure includes a first sidewall and a second sidewall opposite the first sidewall, the first source/drain region is positioned adjacent to the first sidewall of the gate structure, and the second source/drain region is positioned adjacent to the second sidewall of the gate structure. The first source/drain region has a first width, and the second source/drain region has a second width that is greater than the first width.