公开(公告)号：US11095329B1

公开(公告)日：2021-08-17

申请号：US16853969

申请日：2020-04-21

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ahmad Alagry ,  Mustapha Slamani

IPC: H04B1/18 ,  H03H11/34 ,  H04B17/00 ,  H04B1/10 ,  H04B1/00

Abstract: Disclosed is a filter and amplification circuit including a first switch with a single input and multiple outputs, a second switch with multiple inputs and a single output, and signal paths (each with an amplifier and band pass filter) between the outputs of the first switch and the inputs of the second switch, respectively. During filtering, the input of the first switch receives a radio frequency (RF) signal and filtering is performed through a combination of a selected signal path (which is active and has its amplifier enabled) and non-selected signal paths (which are passively coupled to the selected signal path and have their amplifiers disabled). Isolation is provided by the switches (e.g., solid-state switches) and the amplifiers, ensuring that the filtered RF signal at the single output of the second switch has a desired high spurious-free dynamic range (SFDR). Also disclosed are a test system and associated methods.

公开(公告)号：US10949005B2

公开(公告)日：2021-03-16

申请号：US16429702

申请日：2019-06-03

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Mustapha Slamani ,  Kaushal Kannan ,  Ritin Nambiar ,  Timothy M. Platt

IPC: H04B3/46 ,  G06F3/041 ,  H04L7/02 ,  G06F3/0484

Abstract: The present disclosure relates to a testing device and techniques of testing semiconductor structures and, more particularly, to an absolute phase measurement testing device and technique of testing semiconductor structures. The structure includes: a first frequency input source which provides a first signal to an up-converter at an input side of a test fixture; a down-converter on an output side of the test fixture; a second frequency signal source which provides a second signal at a higher frequency than the first signal to the up-converter and the down-converter on the output side of the test fixture; a bypass path which bypasses the test fixture and provides connection between the up-converter and the down-converter; and a digitizer that is connected to an output side of the down-converter.