公开(公告)号：US20240097029A1

公开(公告)日：2024-03-21

申请号：US17933304

申请日：2022-09-19

Applicant: GlobalFoundries U.S. Inc.

Inventor： Nan Wu

IPC: H01L29/78 ,  H01L21/225 ,  H01L21/285 ,  H01L21/74 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L29/7831 ,  H01L21/2252 ,  H01L21/28518 ,  H01L21/743 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/45 ,  H01L29/66484 ,  H01L29/6656

Abstract: Disclosed is a structure including a field effect transistor (FET). The FET includes, on an insulator layer above a substrate, source/drain regions and a section of a semiconductor layer extending laterally between the source/drain regions. A primary gate structure is made of the insulator layer and a well region in the substrate opposite at least the section of the semiconductor layer extending laterally between the source/drain regions. One or two secondary gate structures are on the semiconductor layer between and near one or both of the source/drain regions, respectively. The FET can further include a patterned conformal dielectric layer, which is on the center of the semiconductor layer between the source/drain regions, and which extends onto the secondary gate structure(s). Also disclosed are methods of operating the structure by biasing the secondary gate structure(s) to adjust the effective gate length of the FET and methods of forming the structure.

公开(公告)号：US11257672B2

公开(公告)日：2022-02-22

申请号：US15978334

申请日：2018-05-14

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Nan Wu

IPC: H01L21/027 ,  H01L21/475 ,  H01L27/11 ,  H01L21/28

Abstract: The present disclosure provides manufacturing techniques in which the layout pattern of a RAM cell may be obtained on the basis of a single lithography step, followed by a sequence of two deposition processes, thereby resulting in a self-aligned mechanism for providing the most critical lateral dimensions for active regions. In this manner, the smallest pitch of approximately 80 nm and even less may be accomplished with superior device uniformity, while at the same time reducing overall manufacturing complexity.