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公开(公告)号:US11127818B2
公开(公告)日:2021-09-21
申请号:US16526529
申请日:2019-07-30
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Jagar Singh , Srikanth Balaji Samavedam
IPC: H01L29/08 , H01L21/8234 , H01L29/423 , H01L27/088
Abstract: An illustrative device includes a transistor including a first set of fins defined above a substrate, a second set of fins defined above the substrate, and a gate structure embedded in the substrate between the first set of fins and the second set of fins, wherein the first set of fins and the second set of fins are doped with a first dopant type and the substrate is doped with a second dopant type different than the first dopant type.
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公开(公告)号:US20210175370A1
公开(公告)日:2021-06-10
申请号:US16704002
申请日:2019-12-05
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Jagar Singh , Srikanth Balaji Samavedam
IPC: H01L29/872 , H01L29/66
Abstract: One illustrative Schottky diode disclosed herein includes a semiconductor substrate, an anode region and a cathode region. The anode region includes a plurality of first fins with a first vertical height formed in the anode region, wherein an upper surface of the semiconductor substrate is exposed within the anode region. The cathode region includes a plurality of second fins with a second vertical height that is greater than the first vertical height. The device also includes a conductive structure that contacts and engages at least an upper surface of the plurality of first fins in the anode region.
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公开(公告)号:US20210126126A1
公开(公告)日:2021-04-29
申请号:US16662276
申请日:2019-10-24
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Jagar Singh , Luigi Pantisano , Anvitha Shampur , Frank Scott Johnson , Srikanth Balaji Samavedam
IPC: H01L29/78 , H01L21/8238 , H01L27/092 , H01L29/66
Abstract: A semiconductor device is disclosed including a semiconductor layer, a first well doped with dopants of a first conductivity type defined in the semiconductor layer, a second well doped with dopants of a second conductivity type different than the first conductivity type defined in the semiconductor layer adjacent the first well to define a PN junction between the first and second wells, and an isolation structure positioned in the second well. The semiconductor device also includes a first source/drain region positioned in the first well, a second source/drain region positioned in the second well adjacent a first side of the isolation structure, a doped region positioned in the second well adjacent a second side of the isolation structure, and a gate structure positioned above the semiconductor layer, wherein the gate structure vertically overlaps a portion of the doped region.
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公开(公告)号:US11462648B2
公开(公告)日:2022-10-04
申请号:US16704002
申请日:2019-12-05
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Jagar Singh , Srikanth Balaji Samavedam
IPC: H01L29/87 , H01L29/66 , H01L29/872
Abstract: One illustrative Schottky diode disclosed herein includes a semiconductor substrate, an anode region and a cathode region. The anode region includes a plurality of first fins with a first vertical height formed in the anode region, wherein an upper surface of the semiconductor substrate is exposed within the anode region. The cathode region includes a plurality of second fins with a second vertical height that is greater than the first vertical height. The device also includes a conductive structure that contacts and engages at least an upper surface of the plurality of first fins in the anode region.
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公开(公告)号:US11195947B2
公开(公告)日:2021-12-07
申请号:US16662276
申请日:2019-10-24
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Jagar Singh , Luigi Pantisano , Anvitha Shampur , Frank Scott Johnson , Srikanth Balaji Samavedam
IPC: H01L29/78 , H01L21/8238 , H01L29/66 , H01L27/092 , H01L21/761 , H01L21/8234 , H01L29/423 , H01L29/06
Abstract: A semiconductor device is disclosed including a semiconductor layer, a first well doped with dopants of a first conductivity type defined in the semiconductor layer, a second well doped with dopants of a second conductivity type different than the first conductivity type defined in the semiconductor layer adjacent the first well to define a PN junction between the first and second wells, and an isolation structure positioned in the second well. The semiconductor device also includes a first source/drain region positioned in the first well, a second source/drain region positioned in the second well adjacent a first side of the isolation structure, a doped region positioned in the second well adjacent a second side of the isolation structure, and a gate structure positioned above the semiconductor layer, wherein the gate structure vertically overlaps a portion of the doped region.
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