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公开(公告)号:US20240267042A1
公开(公告)日:2024-08-08
申请号:US18158572
申请日:2023-01-24
Applicant: GlobalFoundries U.S. Inc.
Inventor: Thomas G. McKay , Gail B. Katzman
CPC classification number: H03K17/161 , H03K3/012
Abstract: A disclosed structure (e.g., a switch circuit) includes multiple transistors (e.g., on triple wells) connected in series between a first and second nodes. Each transistor can include a primary gate (e.g., a front gate) for controlling the ON/OFF state of the transistor and a secondary gate (e.g., a back gate) for adjusting the VT of the transistor. The switch circuit further includes multiple capacitors (e.g., APMOM capacitors on triple wells), each connected to the second node and to the secondary gate of a corresponding one of the transistors. In advanced semiconductor-on-insulator processing technology platforms, each secondary gate includes a well region within a semiconductor substrate and a corresponding section of an insulator layer, which is on the semiconductor substrate and adjacent to an active device region for the transistor. The capacitors are preselected during design and different capacitances for limiting parasitic secondary gate-to-substrate coupling. Also disclosed are associated methods.
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公开(公告)号:US11211909B2
公开(公告)日:2021-12-28
申请号:US16889840
申请日:2020-06-02
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Qiao Yang , Thomas G. McKay
IPC: H03F3/45
Abstract: An amplifier includes an input transistor pair connected to amplifier input nodes, a complementary transistor pair connected to a common bias, amplifier output nodes connected to the input transistor pair and the complementary transistor pair, and variable capacitors connected between the complementary transistor pair and the amplifier output nodes.
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公开(公告)号:US20210376805A1
公开(公告)日:2021-12-02
申请号:US16889840
申请日:2020-06-02
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Qiao Yang , Thomas G. McKay
IPC: H03F3/45
Abstract: An amplifier includes an input transistor pair connected to amplifier input nodes, a complementary transistor pair connected to a common bias, amplifier output nodes connected to the input transistor pair and the complementary transistor pair, and variable capacitors connected between the complementary transistor pair and the amplifier output nodes.
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