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公开(公告)号:US10695857B2
公开(公告)日:2020-06-30
申请号:US15723679
申请日:2017-10-03
IPC分类号: G06F30/337 , B23K9/095 , G05B19/418 , B23K11/11 , B23K11/25 , B23K11/24 , B23K31/12 , B23K101/00
摘要: A computer-implemented method for reducing spot welds in a parameterized workpiece model includes generating a new design space (DS) from an original spot weld DS. The new DS includes a plurality of spot weld locations from the parameterized workpiece model with the original spot weld DS. The new DS is optimized to have a fewer number of spot weld locations than the original DS. The processor identifies a plurality of offending spot weld locations of the remaining spot weld locations in the new DS and a plurality of conforming spot weld locations of the remaining spot weld locations. The processor removes all but one optimized extension candidate from processor-selected groupings of welds while enforcing a minimum distance requirement. The processor outputs an inter-distance constrained parameterized workpiece model with an optimized extension candidate in each of the plurality of extended DSs to an operatively connected output processor.
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公开(公告)号:US20190099823A1
公开(公告)日:2019-04-04
申请号:US15723679
申请日:2017-10-03
IPC分类号: B23K9/095 , G05B19/418
摘要: A computer-implemented method for reducing spot welds in a parameterized workpiece model includes generating a new design space (DS) from an original spot weld DS. The new DS includes a plurality of spot weld locations from the parameterized workpiece model with the original spot weld DS. The new DS is optimized to have a fewer number of spot weld locations than the original DS. The processor identifies a plurality of offending spot weld locations of the remaining spot weld locations in the new DS and a plurality of conforming spot weld locations of the remaining spot weld locations. The processor removes all but one optimized extension candidate from processor-selected groupings of welds while enforcing a minimum distance requirement. The processor outputs an inter-distance constrained parameterized workpiece model with an optimized extension candidate in each of the plurality of extended DSs to an operatively connected output processor.
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