公开(公告)号：US20240152306A1

公开(公告)日：2024-05-09

申请号：US18281630

申请日：2021-03-12

Applicant: GOOGLE LLC

Inventor： Derek James Basehore ,  Nicholas Jordan Sanders

IPC: G06F3/14 ,  G06T7/70 ,  G06V10/74

CPC classification number: G06F3/14 ,  G06T7/70 ,  G06V10/761

Abstract: A server provides image data including detailed geometry and shading information for one of more objects in a scene from a last known camera orientation and placement (a “first camera view”) and a height map indicating a distance from the first camera view to each pixel of the image. The image data and the height map are collectively referred to as a “parallax pixel map”. A client device receives the parallax pixel map from the server and updates the parallax pixel map based on a current camera orientation and placement (a “first camera view”). The client device projects the updated parallax pixel map onto the image of the scene based on the current camera view to generate a current display frame. The client device then provides the current display frame for display.

公开(公告)号：US20230418748A1

公开(公告)日：2023-12-28

申请号：US18253174

申请日：2020-11-18

Applicant: Google LLC

Inventor： Derek James Basehore ,  Sonny Rao

IPC: G06F12/0811 ,  G06F1/3225 ,  G06F1/324

CPC classification number: G06F12/0811 ,  G06F1/3225 ,  G06F1/324

Abstract: Techniques and apparatuses are described that use transaction queue lengths to alter a clock frequency that controls access to a memory of an electronic device. Techniques include detecting that a transaction queue threshold has been violated, initiating a counter to measure a time duration, determining that the transaction queue threshold continues to be violated for the time duration and, in response, altering the clock frequency that controls access to the memory of the electronic device.

公开(公告)号：US20240303081A1

公开(公告)日：2024-09-12

申请号：US18549853

申请日：2022-01-26

Applicant: Google LLC

Inventor： Derek James Basehore ,  Nicholas Jordan Sanders

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30149 ,  G06F9/30185 ,  G06F9/3822

Abstract: This disclosure describes apparatuses, methods, and techniques for supporting a parallel decode instruction set computer architecture with variable-length instructions. In various aspects, a processor receives an instruction for execution. A decoder identifies multiple fixed-length prefixes in the instruction and identifies multiple variable-length suffixes in the instruction. Each of the multiple fixed-length prefixes is associated with one of the variable-length suffixes. The instruction is then executed based on the plurality of variable-length suffixes. By so doing, the described systems and methods may be implemented in a manner that reduces program size and reduces the required area on the silicon chip.

公开(公告)号：US20230280816A1

公开(公告)日：2023-09-07

申请号：US18006828

申请日：2020-07-27

Applicant: Google LLC

Inventor： Derek James Basehore ,  Nick Sanders

IPC: G06F1/324 ,  H03K5/135

CPC classification number: G06F1/324 ,  H03K5/135

Abstract: This document describes systems and techniques for adaptive frequency control in integrated circuits. In response to operating conditions that permit a lower frequency of a clock signal, the described systems and techniques dynamically reduce the clock frequency without adjusting the frequency of an input clock signal. The clock frequency is decreased by gating a fraction of the input clock signal and stretching the ungated cycles by an offset amount. By dynamically adjusting the clock frequency in this manner, an integrated circuit can change its clock frequency more quickly and maintain the supply voltage closer to a lower voltage limit to reduce power consumption and allow safer operations.