公开(公告)号：US20080250207A1

公开(公告)日：2008-10-09

申请号：US12119375

申请日：2008-05-12

申请人： GORDON T. DAVIS ,  Richard W. Doing ,  John D. Jabusch ,  M.V.V. Anil Krishna ,  Brett Olsson ,  Eric F. Robinson ,  Sumedh W. Sathaye ,  Jeffrey R. Summers

发明人： GORDON T. DAVIS ,  Richard W. Doing ,  John D. Jabusch ,  M.V.V. Anil Krishna ,  Brett Olsson ,  Eric F. Robinson ,  Sumedh W. Sathaye ,  Jeffrey R. Summers

IPC分类号： G06F12/00

CPC分类号： G06F9/3844 ,  G06F9/3808 ,  G06F12/0875 ,  G06F12/127 ,  G06F2212/1021 ,  G06F2212/1044

摘要： A single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines. Control is exercised over which lines are contained within the cache. This invention avoids inefficiencies in the cache by removing trace lines experiencing early exits from the cache, or trace lines that are short, by maintaining a few bits of information about the accuracy of the control flow in a trace cache line and using that information in addition to the LRU (Least Recently Used) bits that maintain the recency information of a cache line, in order to make a replacement decision.

摘要翻译： 单个统一的一级指令高速缓存，其中一些行可以包含跟踪和同一同余类中的其他行可以包含与常规高速缓存行一致的指令块。 对缓存中包含哪些行进行控制。 本发明通过在跟踪高速缓存行中维护关于控制流的准确度的几位信息并且使用该信息来避免高速缓存中的低效率，通过删除经历来自缓存的早期退出的跟踪线或短路的跟踪线 到保持高速缓存行的新近度信息的LRU（最近使用的）位，以便进行替换判定。

公开(公告)号：US20080250205A1

公开(公告)日：2008-10-09

申请号：US12116676

申请日：2008-05-07

申请人： GORDON T. DAVIS ,  Richard W. Doing ,  John D. Jabusch ,  M VV A. Krishna ,  Brett Olsson ,  Eric F. Robinson ,  Sumedh W. Sathaye ,  Jeffrey R. Summers

发明人： GORDON T. DAVIS ,  Richard W. Doing ,  John D. Jabusch ,  M VV A. Krishna ,  Brett Olsson ,  Eric F. Robinson ,  Sumedh W. Sathaye ,  Jeffrey R. Summers

IPC分类号： G06F12/00 ,  G06N5/02

CPC分类号： G06F12/0864 ,  G06F12/0875 ,  G06F12/0897 ,  G06F2212/6082

摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for a single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines is provided. A mechanism is described for indexing into the cache, and selecting the desired line. Control is exercised over which lines are contained within the cache. Provision is made for selection between a trace line and a conventional line when both match during a tag compare step.

摘要翻译： 体现在用于设计，制造和/或测试用于单个统一级别的一个指令高速缓存的机器可读存储介质中的设计结构，其中一些行可以包含跟踪和相同同余类中的其他行的设计可以包含一致的指令块 提供常规的高速缓存线。 描述了一种用于索引到缓存中并选择所需行的机制。 对缓存中包含哪些行进行控制。 当在标签比较步骤中匹配时，提供在轨迹线和常规线之间的选择。

公开(公告)号：US20080235500A1

公开(公告)日：2008-09-25

申请号：US12131442

申请日：2008-06-02

申请人： GORDON T. DAVIS ,  Richard W. Doing ,  John D. Jabusch ,  M. V.V. Anil Krishna ,  Brett Olsson ,  Eric F. Robinson ,  Sumedh W. Sathaye ,  Jeffrey R. Summers

发明人： GORDON T. DAVIS ,  Richard W. Doing ,  John D. Jabusch ,  M. V.V. Anil Krishna ,  Brett Olsson ,  Eric F. Robinson ,  Sumedh W. Sathaye ,  Jeffrey R. Summers

IPC分类号： G06F9/30

CPC分类号： G06F12/0875 ,  G06F9/3806 ,  G06F9/3808 ,  G06F9/3844

摘要： A design structure embodied in a machine readable storage medium for at least one of designing, manufacturing, and testing a design for a single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines is provided. Instruction branches are predicted taken or not taken using a highly accurate branch history table (BHT). Branches that are predicted not taken are appended to a trace buffer and the next basic block is constructed from the remaining instructions in the fetch buffer. Branches that are predicted taken flush the remaining fetch buffer and the next address is determined using a Branch Target Address Register (BTAC).

摘要翻译： 体现在机器可读存储介质中的设计结构，用于至少一个设计，制造和测试用于单个统一的一级指令高速缓存的设计，其中一些行可以包含跟踪和相同同余类中的其他行的设计可以包含 提供与常规高速缓存线一致的指令。 使用高度精确的分支历史表（BHT）预测采取或不采用指令分支。 预测未采用的分支被附加到跟踪缓冲区，并且下一个基本块是从获取缓冲区中的其余指令构建的。 预测的分支将刷新剩余的获取缓冲区，并使用分支目标地址寄存器（BTAC）确定下一个地址。