公开(公告)号：US20160307886A1

公开(公告)日：2016-10-20

申请号：US15131309

申请日：2016-04-18

Applicant: GaN Systems Inc.

Inventor： John ROBERTS ,  Hugues LAFONTAINE

IPC: H01L27/02 ,  H01L29/778 ,  H01L29/20

CPC classification number: H01L27/0248

Abstract: An integrated gate protection device P for a GaN power transistor D1 provides negative ESD spike protection. Protection device P comprises a smaller gate width wg enhancement mode GaN transistor Pm. The source of Pm is connected to its gate, the drain of Pm is connected to the gate input of D1, and the source of Pm is connected to the intrinsic source of D1. When the gate input voltage is taken negative below the threshold voltage for reverse conduction, Pm conducts and quenches negative voltage spikes. When device P comprises a plurality of GaN protection transistors P1 to Pn, connected in series, it turns on when the gate input voltage applied to the drain of P1 goes negative by more than the sum of the threshold voltages of P1 to Pn. The combined gate width of P1 to Pn is selected to limit the gate voltage excursion of D1.

Abstract translation: 用于GaN功率晶体管D1的集成栅极保护器件P提供负的ESD尖峰保护。 保护器件P包括较小的栅极宽度wg增强型GaN晶体管Pm。 Pm的源极连接到其栅极，Pm的漏极连接到D1的栅极输入，Pm的源极连接到D1的本源。 当门极输入电压为负极低于阈值电压进行反向导通时，Pm导通并熄灭负电压尖峰。 当器件P包括串联连接的多个GaN保护晶体管P1至Pn时，当施加到P1的漏极的栅极输入电压变为负大于P1至Pn的阈值电压之和时，其导通。 选择P1到Pn的组合栅极宽度来限制D1的栅极电压偏移。