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    GATE INPUT PROTECTON FOR DEVICES AND SYSTEMS COMPRISING HIGH POWER E-MODE GaN TRANSISTORS
    1.
    发明申请
    GATE INPUT PROTECTON FOR DEVICES AND SYSTEMS COMPRISING HIGH POWER E-MODE GaN TRANSISTORS 审中-公开
    用于包含高功率E型GaN晶体管的器件和系统的栅极输入保护

    公开(公告)号：US20160307886A1

    公开(公告)日：2016-10-20

    申请号：US15131309

    申请日：2016-04-18

    Applicant: GaN Systems Inc.

    Inventor： John ROBERTS ,  Hugues LAFONTAINE

    IPC: H01L27/02 ,  H01L29/778 ,  H01L29/20

    CPC classification number: H01L27/0248

    Abstract: An integrated gate protection device P for a GaN power transistor D1 provides negative ESD spike protection. Protection device P comprises a smaller gate width wg enhancement mode GaN transistor Pm. The source of Pm is connected to its gate, the drain of Pm is connected to the gate input of D1, and the source of Pm is connected to the intrinsic source of D1. When the gate input voltage is taken negative below the threshold voltage for reverse conduction, Pm conducts and quenches negative voltage spikes. When device P comprises a plurality of GaN protection transistors P1 to Pn, connected in series, it turns on when the gate input voltage applied to the drain of P1 goes negative by more than the sum of the threshold voltages of P1 to Pn. The combined gate width of P1 to Pn is selected to limit the gate voltage excursion of D1.

    Abstract translation: 用于GaN功率晶体管D1的集成栅极保护器件P提供负的ESD尖峰保护。 保护器件P包括较小的栅极宽度wg增强型GaN晶体管Pm。 Pm的源极连接到其栅极，Pm的漏极连接到D1的栅极输入，Pm的源极连接到D1的本源。 当门极输入电压为负极低于阈值电压进行反向导通时，Pm导通并熄灭负电压尖峰。 当器件P包括串联连接的多个GaN保护晶体管P1至Pn时，当施加到P1的漏极的栅极输入电压变为负大于P1至Pn的阈值电压之和时，其导通。 选择P1到Pn的组合栅极宽度来限制D1的栅极电压偏移。

    POWER SWITCHING SYSTEMS COMPRISING HIGH POWER E-MODE GaN TRANSISTORS AND DRIVER CIRCUITRY
    2.
    发明申请
    POWER SWITCHING SYSTEMS COMPRISING HIGH POWER E-MODE GaN TRANSISTORS AND DRIVER CIRCUITRY 有权
    包含高功率E型GaN晶体管和驱动电路的电源开关系统

    公开(公告)号：US20160233859A1

    公开(公告)日：2016-08-11

    申请号：US15099459

    申请日：2016-04-14

    Applicant: GaN Systems Inc.

    Inventor： John ROBERTS ,  Iian H. SCOTT

    IPC: H03K17/687 ,  H01L29/20 ,  H03K5/08 ,  H01L29/778

    CPC classification number: H03K17/687 ,  H01L27/0605 ,  H01L27/085 ,  H01L29/2003 ,  H01L29/7787 ,  H03K5/08 ,  H03K17/04123 ,  H03K2217/0036

    Abstract: Driver circuitry for switching systems comprising enhancement mode (E-Mode) GaN power transistors with low threshold voltage is disclosed. An E-Mode high electron mobility transistor (HEMT) D3 has a monolithically integrated GaN driver, comprising smaller E-Mode GaN HEMTs D1 and D2, and a discrete dual-voltage pre-driver. In operation, D1 provides the gate drive voltage to the gate of the GaN switch D3, and D2 clamps the gate of the GaN switch D3 to the source, via an internal source-sense connection closely coupling the source of D3 and the source of D2. An additional source-sense connection is provided for the pre-driver. Boosting the drive voltage to the gate of D1 produces firm and rapid pull-up of D1 and D3 for improved switching performance at higher switching speeds. High current handling components of the driver circuitry are integrated with the GaN switch and closely coupled to reduce inductance, while the discrete pre-driver can be thermally separated from the GaN chip.

    Abstract translation: 公开了包括具有低阈值电压的增强模式（E模式）GaN功率晶体管的开关系统的驱动电路。 E模式高电子迁移率晶体管（HEMT）D3具有单片集成的GaN驱动器，其包括更小的E型GaN HEMT D1和D2以及分立的双电压预驱动器。 在操作中，D1将栅极驱动电压提供给GaN开关D3的栅极，并且D2通过紧密耦合D3源和D2源的内部源极检测连接将GaN开关D3的栅极钳位到源极 。 为前置驱动程序提供了额外的源感测连接。 将D1和D3的驱动电压提升到D1的栅极，可以实现更快速的D1和D3上拉，从而提高开关速度下的开关性能。 驱动器电路的大电流处理部件与GaN开关集成，并且紧密耦合以减小电感，而离散预驱动器可以与GaN芯片热分离。

    GaN SEMICONDUCTOR DEVICE STRUCTURE AND METHOD OF FABRICATION BY SUBSTRATE REPLACEMENT
    3.
    发明申请
    GaN SEMICONDUCTOR DEVICE STRUCTURE AND METHOD OF FABRICATION BY SUBSTRATE REPLACEMENT 有权
    GaN半导体器件结构和通过衬底替代制造的方法

    公开(公告)号：US20160380090A1

    公开(公告)日：2016-12-29

    申请号：US15078023

    申请日：2016-03-23

    Applicant: GaN Systems Inc.

    Inventor： John ROBERTS ,  Greg P. KLOWAK ,  Cameron MCKNIGHT-MACNEIL

    IPC: H01L29/778 ,  H01L29/205 ,  H01L21/66 ,  H01L23/528 ,  H01L29/06 ,  H01L29/40 ,  H01L23/34 ,  H01L29/20 ,  H01L27/095

    CPC classification number: H01L23/528 ,  H01L22/32 ,  H01L23/36 ,  H01L23/3737 ,  H01L27/095 ,  H01L29/0619 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/7786

    Abstract: Devices and systems comprising high current/high voltage GaN semiconductor devices are disclosed. A GaN die, comprising a lateral GaN transistor, is sandwiched between an overlying header and an underlying composite thermal dielectric layer. Fabrication comprises providing a conventional GaN device structure fabricated on a low cost silicon substrate (GaN-on-Si die), mechanically and electrically attaching source, drain and gate contact pads of the GaN-on-Si die to corresponding contact areas of conductive tracks of the header, then entirely removing the silicon substrate. The exposed substrate-surface of the epi-layer stack is coated with the composite dielectric thermal layer. Preferably, the header comprises a ceramic dielectric support layer having a CTE matched to the GaN epi-layer stack. The thermal dielectric layer comprises a high dielectric strength thermoplastic polymer and a dielectric filler having a high thermal conductivity. This structure offers improved electrical breakdown resistance and effective thermal dissipation compared to conventional GaN-on-Si device structures.

    Abstract translation: 公开了包括高电流/高电压GaN半导体器件的器件和系统。 包括横向GaN晶体管的GaN管芯夹在上覆的集管和下面的复合热介电层之间。 制造包括提供在低成本硅衬底（GaN-on-Si裸片）上制造的常规GaN器件结构，将GaN-Si衬底管芯的源极，漏极和栅极接触焊盘机械地和电连接到导电轨道的相应接触区域 的头部，然后完全去除硅衬底。 外延层堆叠的暴露的基底表面涂覆有复合介电热层。 优选地，集管包括具有与GaN外延层堆叠匹配的CTE的陶瓷电介质支撑层。 热介电层包括高介电强度的热塑性聚合物和具有高导热性的介电填料。 与常规的GaN-on器件结构相比，该结构提供了改进的电击穿电阻和有效的散热。

    DISTRIBUTED DRIVER CIRCUITRY INTEGRATED WITH GaN POWER TRANSISTORS
    5.
    发明申请
    DISTRIBUTED DRIVER CIRCUITRY INTEGRATED WITH GaN POWER TRANSISTORS 有权
    分布式驱动电路与GaN功率晶体管集成

    公开(公告)号：US20160301408A1

    公开(公告)日：2016-10-13

    申请号：US15091867

    申请日：2016-04-06

    Applicant: GaN Systems Inc.

    Inventor： John ROBERTS ,  Ahmad MIZAN

    IPC: H03K17/687 ,  H01L29/20

    CPC classification number: H03K17/162 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41758 ,  H03K17/168 ,  H03K17/6877

    Abstract: Power switching systems are disclosed comprising driver circuitry for enhancement-mode (E-Mode) GaN power transistors with low threshold voltage. Preferably, a GaN power switch (D3) comprises an E-Mode high electron mobility transistor (HEMT) with a monolithically integrated GaN driver. D3 is partitioned into sections. At least the pull-down and, optionally, the pull-up driver circuitry is similarly partitioned as a plurality of driver elements, each driving a respective section of D3. Each driver element is placed in proximity to a respective section of D3, reducing interconnect track length and loop inductance. In preferred embodiments, the layout of GaN transistor switch and the driver elements, dimensions and routing of the interconnect tracks are selected to further reduce loop inductance and optimize performance. Distributed driver circuitry integrated on-chip with one or more high power E-Mode GaN switches allows closer coupling of the driver circuitry and the GaN switches to reduce effects of parasitic inductances.

    Abstract translation: 公开了包括具有低阈值电压的增强型（E模））GaN功率晶体管的驱动电路的电源开关系统。 优选地，GaN功率开关（D3）包括具有单片集成GaN驱动器的E模式高电子迁移率晶体管（HEMT）。 D3被划分为几个部分。 至少下拉和可选地，上拉驱动器电路被类似地划分为多个驱动器元件，每个驱动器元件驱动D3的相应部分。 每个驱动器元件放置在D3的相应部分附近，减少了互连轨道长度和环路电感。 在优选实施例中，选择GaN晶体管开关的布局和驱动元件，互连轨道的尺寸和布线，以进一步降低环路电感并优化性能。 集成片上与一个或多个高功率E-Mode GaN开关的分布式驱动器电路允许驱动电路和GaN开关的更紧密耦合，以减少寄生电感的影响。

    EMBEDDED PACKAGING FOR DEVICES AND SYSTEMS COMPRISING LATERAL GaN POWER TRANSISTORS
    6.
    发明申请
    EMBEDDED PACKAGING FOR DEVICES AND SYSTEMS COMPRISING LATERAL GaN POWER TRANSISTORS 有权
    嵌入式封装用于包含侧向GaN功率晶体管的器件和系统

    公开(公告)号：US20160240471A1

    公开(公告)日：2016-08-18

    申请号：US15027012

    申请日：2015-04-15

    Applicant: GaN Systems Inc.

    Inventor： Greg P. KLOWAK ,  Ahmad MIZAN ,  John ROBERTS

    IPC: H01L23/498 ,  H01L23/522 ,  H01L29/20 ,  H01L23/532 ,  H01L29/78 ,  H01L23/482

    CPC classification number: H01L23/49844 ,  H01L23/3107 ,  H01L23/4824 ,  H01L23/5226 ,  H01L23/53228 ,  H01L24/19 ,  H01L24/20 ,  H01L29/2003 ,  H01L29/778 ,  H01L29/78 ,  H01L2224/04105 ,  H01L2224/18 ,  H01L2224/2518 ,  H01L2224/82

    Abstract: Embedded packaging for devices and systems comprising lateral GaN power transistors is disclosed. The packaging assembly is suitable for large area, high power GaN transistors and comprises an assembly of a GaN power transistor and package components comprising a three level interconnect structure. In preferred embodiments, the three level interconnect structure comprises an on-chip metal layer, a copper redistribution layer and package metal layers, in which there is a graduated or tapered contact area sizing through the three levels for dividing/applying current on-chip and combining/collecting current off-chip, with distributed contacts over the active area of the GaN power device. This embedded packaging assembly provides a low inductance, low resistance interconnect structure suitable for devices and systems comprising large area, high power GaN transistors for high voltage/high current applications.

    Abstract translation: 公开了包括横向GaN功率晶体管的器件和系统的嵌入式封装。 包装组件适用于大面积高功率GaN晶体管，并且包括GaN功率晶体管和包括三级互连结构的封装组件的组件。 在优选实施例中，三电平互连结构包括片上金属层，铜再分布层和封装金属层，其中存在通过三个级别分级/施加电流片上的刻度或锥形接触面积， 在GaN功率器件的有源区域上结合/收集芯片外的电流与分布式触点。 该嵌入式封装组件提供适合于用于高电压/高电流应用的大面积高功率GaN晶体管的器件和系统的低电感，低电阻互连结构。

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